Using time-aware memory sensing to address resistance drift issue in multi-level phase change memory

Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010

Volumn , Issue , 2010, Pages 356-361

  Xu, Wei ^a   Zhang, Tong ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

BCH; LDPC; Multi level phase change memory; Structural relaxation; Time aware sensing

Indexed keywords

BASIC IDEA; BCH; BCH CODE; DECISION TIME; ERROR CORRECTION CODES; LDPC; LDPC CODES; LOG LIKELIHOOD; MEMORY STORAGE; MULTI-LEVEL; NEGATIVE IMPACTS; ORDERS OF MAGNITUDE; SENSING CONFIGURATION; STATIC MEMORY; TIME-DEPENDENT;

CODING ERRORS; ERROR CORRECTION; IMPACT RESISTANCE; STRUCTURAL RELAXATION;

PHASE CHANGE MEMORY;

EID: 77952661652     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2010.5450549     Document Type: Conference Paper

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