A durable and energy efficient main memory using phase change memory technology

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2009, Pages 14-23

  Zhou, Ping ^a   Zhao, Bo ^a   Yang, Jun ^a   Zhang, Youtao ^b  

^a University of Pittsburgh   (United States)

^b University of Pittsburgh   (United States)

Author keywords

Endurance; Low power; Phase change memory

Indexed keywords

ACCESS LATENCY; DRAM TECHNOLOGY; DYNAMIC POWER; ENDURANCE; ENERGY CONSUMPTION; ENERGY EFFICIENT; LEAKAGE POWER; LOW LEVEL; LOW POWER; MAIN MEMORY; MEMORY CELL; MEMORY HIERARCHY; NON-VOLATILE MEMORIES; NON-VOLATILE MEMORY TECHNOLOGY; PHASE-CHANGE MEMORY TECHNOLOGIES; TOTAL ENERGY;

COMPUTER ARCHITECTURE; COMPUTERS; DURABILITY; DYNAMIC RANDOM ACCESS STORAGE; ENERGY EFFICIENCY; PULSE CODE MODULATION; TECHNOLOGY;

PHASE CHANGE MEMORY;

EID: 70450277571     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1555754.1555759     Document Type: Conference Paper

References (31)

1. F. Bedeschi, et al. "A Multi-Level-Cell Bipolar-Selected Phase-Change Memory," 2008 IEEE International Solid-State Circuits Conference, pp. 428-429, 2008.
2. B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. Loh, D. McCaule, P. Morrow, D. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, C. Webb, "Die Stacking (3D) Microarchitecture," International Symposium on Microarchitecture, pp. 469-479, 2006.
3. th International Symposium on Low Power Electronics and Design, pp. 412-417, 2006.
4. Y. C. Chen, et al. "Ultra-Thin Phase-Change Bridge Memory Device Using GeSb," International Electron Devices Meeting, pp. 777-780, December 2006.
5. S. L. Cho, et al., "Highly Scalable On-axis Confined Cell Structure for High Density PRAM beyond 256Mb," Symposium on VLSI Technology Digest of Technical Papers, pp. 96-97, 2005.
6. W. Y. Cho, et al. "A 0.18-um 3.0-V 64-Mb Nonvolatile Phase-Transition Random Access Memory (PRAM)," IEEE Journal of Solid-State-Circuits, Vol. 40, No. 1, pp. 293-300, 2005.
7. X. Dong, X. Wu, G. Sun, Y. Xie, H. Li, Y. Chen, "Circuit and Microarchitecture Evaluation of 3D Stacking Magnetic RAM (MRAM) as a Universal Memory Replacement," Design Automation Conference, pp. 554-559, 2008.
8. M. Kanellos, "IBM Changes Directions in Magnetic Memory," August, 2007, http://news.cnet.com/IBM-changes-directions-in-magnetic-memory/ 2100-1004-3-6203198.html
9. D. H. Kang, et al., "Two-bit Cell Operation in Diode-Switch Phase Change Memory Cells with 90nm Technology," IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 98-99, 2008.
10. S. Kang, et al. "A 0.1-μm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) with 66-MHz Synchronous Burst-Read Operation," IEEE Journal of Solid-State Circuits, pp. 210-218, Vol. 42, No. 1, Jan. 2007.
11. th International Symposium on Computer Architecture, pp. 327-338, 2008.
12. T. Kgil, A. Saidi, N. Binkert, R. Dreslinski, S. Reinhardt, K. Flautner, T. Mudge, "PicoServer: Using 3D Stacking Technology to Enable a Compact Energy Efficient Chip Multiprocessor," International Conference on Architecture Support for Programming Languages and Operating Systems, pp. 117-128, 2006.
13. S. Kim, H.-S. P. Wong, "Generalized Phase Change Memory Scaling Rule Analysis," Non-Volatile Semiconductor Memory Workshop, 2006.
14. S. Lai, T. Lowrey, "OUM - A 180nm Nonvolatile Memory Cell Element Technology for Standalone and Embedded Applications," International Electron Devices Meeting, pp. 36.5.1-36.5.4, 2001.
15. K.-J. Lee, et al. "A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput," IEEE Journal of Solid-state Circuits, pp. 150-162, Vol. 43, No. 1, January 2008.
16. K. M. Lepak and M. H. Lipasti, "On the Value Locality of Store Instructions," International Symposium on Computer Architecture, pp. 182-191, 2000.
17. K. M. Lepak and M. H. Lipasti, "Silent Stores for Free," International Symposium on Microarchitecture, pp. 22-31, 2000.
18. th International Symposium on Computer Architecture, pp. 453-464, 2008.
19. th International Conference on VLSI Design, pp. 108-112, 2006.
20. H. Oh, et al. "Enhanced Write Performance of a 64-Mb Phase-Change Random Access Memory," IEEE Journal of Solid-State-Circuits, Vol. 41, No. 1, pp. 122-126, 2006.
21. J. H. Oh, et al. "Full Integration of Highly Manufacturable 512Mb PRAM Based on 90nm Technology," International Electron Devices Meeting, pp. 49-52, 2006.
22. A. Pirovano, A. Lacaita, A. Benvenuti, F. Pellizzer, S. Hudgens, R. Bez, "Scaling Analysis of Phase-Change Memory Technology," IEEE International Electron Devices Meeting, pp. 29.6.1-29.6.4, 2003.
23. S Raoux, et al., "Phase-Change Random Access Memory: A Scalable Technology," IBM Journal of Research and Development, vol. 52, No. 4/5, pp. 465-479, 2008.
24. F. Tabrizi, "The Future of Scalable STT-RAM as a Universal Embedded Memory," Embedded.com, February 2007.
25. th International Symposium on Computer Architecture, pp. 51-62, 2008.
26. M. Wu, W. Zwaenepoel, "eNVy: A Nonvolatile, Main Memory Storage System," International Conference on Architecture Support for Programming Languages and Operating Systems, pp. 86-97, 1994.
27. 5 Confined Structures and Integration of 64Mb Phase-Change Random Access Memory," Japanese Journal of Applied Physics, pp. 2691-2695, 2005.
28. Intel, "Intel, STMicroelectronics Deliver Industry's First Phase Change Memory Prototypes," Intel News Release, Feb. 6, 2008, http://www.intel.com/pressroom/archive/releases/20080206corp.htm
29. Milo M. K. Martin, et al., "Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset," Computer Architecture News (CAN), 2005.
30. P. S. Magnusson, et al., "Simics: A full system simulation platform," Computer, 35(2):50-58, 2002.
31. "The International Technology Roadmap for Semiconductors, Process Integration, Device and Structures," http://www.itrs.net/links/2007itrs/ 2007chapters/2007PIDS.pdf 2007.