-
1
-
-
21644479869
-
Highly Manufacturable High Density Phase Change Memory of 64Mb and Beyond
-
May
-
S. J. Ahn et al. "Highly Manufacturable High Density Phase Change Memory of 64Mb and Beyond," Proc. Int'l Electron Devices Meeting (IEDM), May 2004.
-
(2004)
Proc. Int'l Electron Devices Meeting (IEDM)
-
-
Ahn, S.J.1
-
3
-
-
55849111933
-
TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation
-
September
-
S. Cho, S. Demetriades, S. Evans, L. Jin, H. Lee, K. Lee, and M. Moeng. "TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation," Proc. Int'l Conf. Parallel Processing (ICPP), September 2008.
-
(2008)
Proc. Int'l Conf. Parallel Processing (ICPP)
-
-
Cho, S.1
Demetriades, S.2
Evans, S.3
Jin, L.4
Lee, H.5
Lee, K.6
Moeng, M.7
-
5
-
-
34548861504
-
A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100ìA Cell Write Current
-
February
-
S. Hanzawa et al. "A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100ìA Cell Write Current," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC), February 2007.
-
(2007)
Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC)
-
-
Hanzawa, S.1
-
6
-
-
84879993852
-
-
Intel. Intel Atom Processor, http://www.intel.com/technology/atom/ .
-
Intel Atom Processor
-
-
-
14
-
-
27644488999
-
A Case for Asymmetric-Cell Cache Memories
-
July
-
A. Moshovos, B. Falsa., F. N. Najm, and N. Azizi. "A Case for Asymmetric-Cell Cache Memories," IEEE Trans. Very Large Scale Integration Systems (TVLSI), 13(7), July 2005.
-
(2005)
IEEE Trans. Very Large Scale Integration Systems (TVLSI)
, vol.13
, Issue.7
-
-
Moshovos, A.1
Falsa, B.2
Najm, F.N.3
Azizi, N.4
-
16
-
-
76749150335
-
-
Nero AG. http://www.nero.com.
-
Nero AG
-
-
-
17
-
-
76749136120
-
Pictures of the Day
-
New York Times. Pictures of the Day, http://www.nytimes.com/pages/ multimedia/.
-
New York Times
-
-
-
20
-
-
55449106208
-
Phase-change random access memory: A scalable technology
-
July/September
-
S. Raoux et al. "Phase-change random access memory: A scalable technology." IBM J. Res. & Dev., 52(4/5), July/September 2008.
-
(2008)
IBM J. Res. & Dev
, vol.52
, Issue.4-5
-
-
Raoux, S.1
-
21
-
-
25844437046
-
POWER5 system microarchitecture
-
July/September
-
B. Sinharoy et al. "POWER5 system microarchitecture," IBM J. Res. & Dev., 49(4/5), July/September 2005.
-
(2005)
IBM J. Res. & Dev
, vol.49
, Issue.4-5
-
-
Sinharoy, B.1
-
22
-
-
76749116053
-
-
Standard Performance Evaluation Corporation
-
Standard Performance Evaluation Corporation. http://www.specbench.org.
-
-
-
-
23
-
-
0029179077
-
The SPLASH-2 Programs: Characterization and Methodological Considerations
-
June
-
S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. "The SPLASH-2 Programs: Characterization and Methodological Considerations," Proc. Int'l Symp. Computer Architecture (ISCA), June 1995.
-
(1995)
Proc. Int'l Symp. Computer Architecture (ISCA)
-
-
Woo, S.C.1
Ohara, M.2
Torrie, E.3
Singh, J.P.4
Gupta, A.5
-
24
-
-
34548825142
-
A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme
-
May
-
B.-D. Yang et al. "A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme," Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS), May 2007.
-
(2007)
Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS)
-
-
Yang, B.-D.1
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