Improving read performance of phase change memories via write cancellation and write pausing

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2010, Pages

  Qureshi, Moinuddin K ^a   Franceschini, Michele M ^a   Lastras Montaño, Luis A ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; ITERATIVE METHODS; MEMORY ARCHITECTURE; SUPERCOMPUTERS;

BASELINE SYSTEMS; COST EFFECTIVE; LATENCY INCREASE; PERFORMANCE DEGRADATION; PHASE CHANGE MEMORY (PCM); PRIORITY SCHEDULING; READ LATENCIES; READ PERFORMANCE;

PHASE CHANGE MEMORY;

EID: 77952570744     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/hpca.2010.5416645     Document Type: Conference Paper

References (21)

1. F. Bedeschi et al. A bipolar-selected phase change memory featuring multi-level cell storage. IEEE Journal of Solid-State Circuits, 44(1):217-227, 2009.
2. C. Dirik and B. Jacob. The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization. In ISCA'09, 2009.
3. R. Freitas and W. Wilcke. Storage-class memory: The next storage system technology. IBM Journal of R. and D., 52(4/5), 2008.
4. JEDEC Solid State Technology Assoc. Low power double data rate 2 (LPDDR2): JESD209-2. March 2009.
5. T. Kgil, D. Roberts, and T. Mudge. Improving nand flash based disk caches. In ISCA'08, pages 327-338, 2008.
6. B. Lee, E. Ipek, O.Mutlu, and D. Burger. Architecting phase change memory as a scalable DRAM alternative. In ISCA-36, 2009.
7. C. Lefurgy et al. Energy management for commercial servers. IEEE Computer, 36(12):39-48, Dec. 2003.
8. D. Mantegazza, D. Ielmini, E. Varesi, A. Pirovano, and A. Lacaita. Statistical analysis and modeling of programming and retention in PCM arrays. In IEEE International Electron Devices Meeting, 2007.
9. O. Mutlu and T. Moscibroda. Stall-time fair memory access scheduling for chip multiprocessors. In MICRO-40, 2007.
10. O. Mutlu and T. Moscibroda. Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared dram systems. In ISCA-35, 2008.
11. T. Nirschl et al. Write strategies for 2 and 4-bit multi-level phase-change memory. In IEDM '07: Proceedings of the 2007 IEEE International Electron Devices Meeting, 2007.
12. E. Perelman et al. Using SimPoint for accurate and efficient simulation. ACM SIGMETRICS Perf. Eval. Review, 31(1):318-319, 2003.
13. M. Qureshi et al. Scalable high performance main memory system using phase-change memory technology. In ISCA-36, 2009.
14. S. Raoux et al. Phase-change random access memory: A scalable technology. IBM Journal of R. and D., 52(4/5):465-479, 2008.
15. S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens. Memory access scheduling. In ISCA-27, pages 128-138, 2000.
16. A. Snavely, D. M. Tullsen, and G. Voelker. Symbiotic job-scheduling with priorities for a simultaneous multithreading processor. In Proceedings of the 2002 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 2002.
17. G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen. A novel architecture of the 3d stacked mram 12 cache for cmps. In IEEE 15th International Symposium on High Performance Computer Architecture, 2009.
18. J. Tominaga et al. Structure of the Optical Phase Change Memory Alloy, AgVInSbTe, Determined by Optical Spectroscopy and Electron Diffraction,. J. Appl. Phys., 82(7), 1997.
19. X. Wu et al. Hybrid cache architecture with disparate memory technologies. In ISCA-36, 2009.
20. N. Yamada, E. Ohno, K. Nishiuchi, and N. Akahira. Rapid-Phase Transitions of GeTe-Sb2Te3 Pseudobinary Amorphous Thin Films for an Optical Disk Memory. J. Appl. Phys., 69(5), 1991.
21. P. Zhou et al. A durable and energy efficient main memory using phase change memory technology. In ISCA-36, 2009.