FREE-p: Protecting non-volatile memory against both hard and soft errors

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2011, Pages 466-477

  Yoon, Doe Hyun ^a   Muralimanohar, Naveen ^b   Chang, Jichuan ^b   Ranganathan, Parthasarathy ^b   Jouppi, Norman P ^b   Erez, Mattan ^a  

^a The University of Texas at Austin   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EMERGING NON-VOLATILE MEMORIES; HIGH COSTS; HIGH-LEVEL FAULT; MEMORY CONTROLLER; NON-VOLATILE MEMORIES; PERFORMANCE DEGRADATION; PHASE-CHANGE RAM; PROCESS VARIATION; REMAPPING; SOFT ERROR;

ERRORS; FAULT TOLERANCE; MEMORY ARCHITECTURE; PHASE CHANGE MEMORY;

RANDOM ACCESS STORAGE;

EID: 79955923054     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2011.5749752     Document Type: Conference Paper

References (36)

1. ITRS 2008 update. Tech. report, Int'l Tech. Roadmap for Semiconductors, 2008.
2. J. H. Ahn, et al. Future scaling of processor-memory interfaces. In SC, 2009.
3. AMD. BIOS and kernel developer's guide for AMD NPT family 0Fh processors, 2007.
4. C. Bienia, et al. The PARSEC benchmark suite: Characterization and architectural implications. Tech. Report TR-811-08, Princeton Univ., 2008.
5. G. W. Burr, et al. Phase change memory technology. J. Vacuum Science and Tech. B, 28 (2): 223-262, 2010.
6. C. L. Chen and M. Y. Hsiao. Error-correcting codes for semiconductor memory applications: A state-of-the-art review. IBM J. Res. and Dev., 28 (2): 124-134, 1984. (Pubitemid 14546564)
7. S. Cho and H. Lee. Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance. In MICRO, 2009.
8. T. J. Dell. System RAS implications of DRAM soft errors. IBM J. Res. and Dev., 52 (3): 307-314, 2008.
9. P. Friedberg, et al. Modeling within-die spatial correlation effects for process-design co-optimization. In ISQED, 2005.
10. E. Ipek, et al. Dynamically replicated memory: Building reliable systems from nanoscale resistive memories. In ASPLOS, 2010.
11. Y. Joo, et al. Energy- and endurance-aware design of phase change memory caches. In DATE, 2010.
12. D.-H. Kang, et al. Two-bit cell operation in diode-switch phase change memory cells with 90nm technology. In Symp. VLSI Tech., 2008.
13. B. C. Lee, et al. Architecting phase change memory as a scalable DRAM alternative. In ISCA, 2009.
14. MICRON. NAND Flash Translation Layer (NFTL) 4.5.0 User Guide, 2010.
15. J. A. Nerl, et al. System and method for controlling application of an error correction code. In U.S. Patent, #7,308,638, 2007.
16. Numonyx. 128-Mbit Parallel Phase Change Memory, 2010.
17. A. Pirovano, et al. Reliability study of phase-change nonvolatile memories. IEEE Tran. Device and Materials Reliability, 4 (3): 422-427, 2004.
18. M. K. Qureshi, et al. Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling. In MICRO, 2009.
19. M. K. Qureshi, et al. Scalable high-performance main memory system using phase-change memory technology. In ISCA, 2009.
20. S. Rixner, et al. Memory access scheduling. In ISCA, 2000.
21. D. Roberts, et al. On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology. In DSD, 2007.
22. S. Schechter, et al. Use ECP, not ECC, for hard failures in resistive memories. In ISCA, 2010.
23. B. Schroeder, et al. DRAM errors in the wild: A large-scale field study. In SIGMETRICS, 2009.
24. N. H. Seong, et al. Security refresh: Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. In ISCA, 2010.
25. N. H. Seong, et al. SAFER: Stuck-at-fault error recovery for memories. In MICRO, 2010.
26. D. Strukov. The area and latency tradeoffs of binary bit-parallel BCH decoders for prospective nanoelectronic memories. In Asilomar Conf., 2006.
27. A. Udipi, et al. Rethinking DRAM design and organization for energy-constrained multi-cores. In ISCA, 2010.
28. C. Wilkerson, et al. Reducing cache power with low-cost, multi-bit error-correcting codes. In ISCA, 2010.
29. C. Wilkerson, et al. Trading off cache capacity for reliability to enable low voltage operation. In ISCA, 2008.
30. S. C. Woo, et al. The SPLASH-2 programs: Characterization and methodological considerations. In ISCA, 1995.
31. B.-D. Yang, et al. A low power phase-change random access memory using a data-comparison write scheme. In ISCAS, 2007.
32. Y. Yokoyama, et al. A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%. In CICC, 2000.
33. D. H. Yoon and M. Erez. Virtualized and flexible ECC for main memory. In ASPLOS, 2010.
34. W. Zhang and T. Li. Characterizing and mitigating the impact of process variations on phase change based memory systems. In MICRO, 2009.
35. Z. Zhang, et al. A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. In MICRO, 2000.
36. P. Zhou, et al. A durable and energy efficient main memory using phase change memory technology. In ISCA, 2009.