Scalable high performance main memory system using phase-change memory technology

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2009, Pages 24-33

  Qureshi, Moinuddin K ^a   Srinivasan, Vijayalakshmi ^a   Rivers, Jude A ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Dram caching; Endurance; Phase change memory; Wear leveling

Indexed keywords

BASELINE SYSTEMS; ENDURANCE; HYBRID MEMORIES; IN-PHASE; LEVEL MODEL; MAIN MEMORY; MEMORY SUBSYSTEMS; MEMORY TECHNOLOGY; PHASE-CHANGE MEMORY TECHNOLOGIES; POWER BUDGETS; POWER CONSTRAINTS; WEAR LEVELING;

BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER CRIME; COMPUTER SYSTEMS; DURABILITY; DYNAMIC RANDOM ACCESS STORAGE; FLASH MEMORY; PULSE CODE MODULATION;

PHASE CHANGE MEMORY;

EID: 70450273507     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1555754.1555760     Document Type: Conference Paper

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