An 8.5 mW continuous-time Δ Σ modulator with 25 MHz bandwidth using digital background DAC linearization to achieve 63.5 dB SNDR and 81 dB SFDR

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 12, 2011, Pages 2869-2881

  Kauffman, John G ^a   Witte, Pascal ^a   Becker, Joachim ^a   Ortmanns, Maurits ^a  

^a UNIVERSITY OF ULM   (Germany)

Author keywords

Analog to digital conversion; background correction; continuous time; DAC error estimation; delta sigma modulation; DS modulation; finite gain bandwidth compensation; low power design; multibit DAC linearization; multibit internal quantization; SD modulation; sigma delta modulation

Indexed keywords

BACKGROUND CORRECTION; CONTINUOUS TIME; GAIN BANDWIDTH; LOW-POWER DESIGN; MULTI-BITS;

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; CMOS INTEGRATED CIRCUITS; CONTINUOUS TIME SYSTEMS; DELTA SIGMA MODULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; LINEARIZATION; MODULATION;

MODULATORS;

EID: 82155172915     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2164303     Document Type: Conference Paper

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