A 20MHz BW 68dB DR CT Δσ ADC based on a multi-bit time-domain quantizer and feedback element

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 174-176

  Dhanasekaran, Vijay ^a,b   Gambhir, Manisha ^a   Elsayed, Mohamed M ^a   Sánchez Sinencio, Edgar ^a   Silva Martinez, Jose ^a   Mishra, Chinmaya ^a,b   Chen, Lei ^a   Pankratz, Erik ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

^b QUALCOMM INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349271262     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977364     Document Type: Conference Paper

References (6)

1. B. Nauta and A.J. Annema, "Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies," European Solid-State Circuits Conf., pp. 45-53, Sept. 2005.
2. Y. Tsividis, "Digital Signal Processing in Continuous Time: A Possibility for Avoiding Aliasing and Reducing Quantization Error," IEEE Int. Conf. Acoustics, Speech, and Signal Processing, vol.II, pp. 589-592, May 2004.
3. M.Z. Straayer and M.H. Perrott, "A 10-bit 20MHz 38mW 950MHz CT Δσ ADC with a 5-bit noise-shaping VCO-based quantizer and DEM circuit in 0.13iμ CMOSIEEE Symp. VLSI Circuits, pp. 246-247, June 2007.
4. V. Dhanasekaran, Baseband Analog Circuits in Deep-Submicron CMOS Technologies Targeted For Mobile Multimedia, Ph.D. Dissertation, Texas A&M University, College Station, TX, Aug. 2008.
5. L.J. Breems et al., "A 56mW CT Quadrature Cascaded Δσ Modulator with 77dB DR in a Near Zero-IF 20MHz Band," ISSCC Dig. Tech. Papers, pp. 238-239, Feb. 2007.
6. P. Malla et al., "A 28mW Spectrum-Sensing Reconfigurable 20MHz 72dB-SNR 70dBSNDR DT Δσ ADC for 802.11n/WiMAX Receivers," ISSCC Dig. Tech. Papers, pp. 496- 497, Feb. 2008.