A 2.1mW/3.2mW delay-compensated GSM/WCDMA ΣΔ analog-digital converter

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 180-181

  Vadipour, Morteza ^a   Chen, Calvin ^a   Yazdi, Ahmad ^a   Nariman, Mohammad ^a   Li, Tom ^a   Kilcoyne, Patrick ^a   Darabi, Hooman ^a  

^a BROADCOM CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; FREQUENCY CONVERTERS; VLSI CIRCUITS;

65NM CMOS TECHNOLOGY; ANALOG-DIGITAL CONVERTER; AREA PENALTY; CONTINUOUS-TIME; DUAL MODES; EXCESS LOOP DELAY; SIGMA-DELTA; SIGMA-DELTA ADC;

CONTINUOUS TIME SYSTEMS;

EID: 51949086959     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4585998     Document Type: Conference Paper

References (5)

1. J. A. Cherry and W. M. Snelgrove,"Excess loop delay in continuous-time delta-sigma modulators" IEEE Trans. Circ. Syst. II, pp. 376-389, April 1999.
2. R. Schreier and G. Temes, Understanding Delta-Sigma Data Converters, IEEE Press 2005.
3. G. Mitteregger et al,"A 20-mW 640-MHz CMOS Continuous-Time ΣΔ ADC with 20-MHz Signal Bandwidth, 80dB Dynamic Range and 12-bit ENOB", IEEE J. Solid-State Circ. , pp.2641-2649 VOL. 41, NO. 12, Dec 2006.
4. T.Christen et al,"A 0.13μm CMOS EDGE/UMTS/WLAN Tri-Mode ΔΣ ADC with -92dB THD" ISSCC Dig. Tech. papers, pp. 240-241, Feb 2007.
5. th-order CT/DT Multi-Mode ΔΣ Modulator" ISSCC Dig. Tech. papers, pp. 244-245, Feb 2007.