A 0.13μm CMOS EDGE/UMTS/WLAN Tri-Mode ΔΣ ADC with -92dB THD

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 240-242

  Christen, Thomas ^a,b   Burger, Thomas ^b   Huang, Qiuting ^a,b  

^a Advanced Circuit Pursuit AG   (Switzerland)

^b ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; SIGNAL ANALYSIS; WIRELESS TELECOMMUNICATION SYSTEMS;

SIGNAL BANDWIDTH; WIRELESS APPLICATIONS; WLAN MODE;

WIRELESS LOCAL AREA NETWORKS (WLAN);

EID: 34548839092     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373383     Document Type: Conference Paper

References (4)

1. T. Burger, Q. Huang, "A 13.5mW, 185MSample/s ΔΣ- Modulator for UMTS/GSM Dual-Standard IF Reception," IEEE J. Solid-State Circuits, vol. 36, pp. 1868-1878, Dec., 2001.
2. R. van Veldhoven, "A Triple-Mode Continuous-Time ΔΣ Modulator With Switched-Capacitor Feedback DAC for a GSM-EDGE/CDMA2000/UMTS Receiver," IEEE J. Solid-Slate Circuits, vol. 38, pp. 2069-2076, Dec., 2003.
3. C. Martelli, R. Reutemann, C. Benkeser, et al., "A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-End," ISSCC Dig. Tech. Papers, pp. 260-261, Feb., 2007.
4. O. Oliaei, P. Clement, P. Gorisse, "A 5mW ΔΣ. Modulator with 84dB Dynamic Range for GSM/EDGE," IEEE J. Solid-State Circuits, vol. 37, pp. 2-10, Jan., 2002.