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Volumn , Issue , 2011, Pages 472-473

An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization

Author keywords

[No Author keywords available]

Indexed keywords

FEEDBACK LINEARIZATION; RADIO TRANSCEIVERS; SURVEYING; TIME DOMAIN ANALYSIS;

EID: 79955721443     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746402     Document Type: Conference Paper
Times cited : (32)

References (8)
  • 1
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    • Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CT ΔΣ for SDR in 90 nm Digital CMOS
    • June
    • P. Crombez, G. van der Plas, M. Steyaert, M. Craninckx, "Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CT ΔΣ for SDR in 90 nm Digital CMOS," IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1159-1171, June, 2010.
    • (2010) IEEE J. Solid-State Circuits , vol.45 , Issue.6 , pp. 1159-1171
    • Crombez, P.1    Van Der Plas, G.2    Steyaert, M.3    Craninckx, M.4
  • 2
    • 58049102887 scopus 로고    scopus 로고
    • A 20.7 mW Continuous-Time Delta-Sigma Modulator with 15 MHz Bandwidth and 70dB Dynamic Range
    • Sept.
    • K.Reddy and S. Pavan, "A 20.7 mW Continuous-Time Delta-Sigma Modulator with 15 MHz Bandwidth and 70dB Dynamic Range," ESSCIRC, pp. 210-213, Sept., 2009.
    • (2009) ESSCIRC , pp. 210-213
    • Reddy, K.1    Pavan, S.2
  • 3
    • 70349283738 scopus 로고    scopus 로고
    • A 0.13μm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-Based Integrator and Quantizer
    • Feb.
    • M. Park and M. Perrott, "A 0.13μm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-Based Integrator and Quantizer," ISSCC Dig. Tech. Papers, pp. 170-171, Feb., 2009.
    • (2009) ISSCC Dig. Tech. Papers , pp. 170-171
    • Park, M.1    Perrott, M.2
  • 4
    • 70349271262 scopus 로고    scopus 로고
    • A 20MHz BW 68dB DR CT ΔΣ ADC Based on a Multi-Bit Time-Domain Quantizer and Feedback Element
    • Feb.
    • V. Dhanasekaran, M. Gambhir, M.M. Elsayed, et al., "A 20MHz BW 68dB DR CT ΔΣ ADC Based on a Multi-Bit Time-Domain Quantizer and Feedback Element," ISSCC Dig. Tech. Papers, pp. 174-175, Feb., 2009.
    • (2009) ISSCC Dig. Tech. Papers , pp. 174-175
    • Dhanasekaran, V.1    Gambhir, M.2    Elsayed, M.M.3
  • 5
    • 34548841783 scopus 로고    scopus 로고
    • A 14b 20mW 640MHz CMOS CT DS ADC with 20MHz Signal Bandwidth and 12b ENOB
    • Feb.
    • G. Mitteregger, C. Ebner, S. Mechnig, et al., "A 14b 20mW 640MHz CMOS CT DS ADC with 20MHz Signal Bandwidth and 12b ENOB," ISSCC Dig. Tech. Papers, pp. 62-63, Feb., 2006.
    • (2006) ISSCC Dig. Tech. Papers , pp. 62-63
    • Mitteregger, G.1    Ebner, C.2    Mechnig, S.3
  • 6
    • 0036050041 scopus 로고    scopus 로고
    • Digital Techniques for Improved ΔΣ Data Conversion
    • May
    • J. Silva, X. Wang, P. Kiss, U.-K. Moon, and G.C. Temes, "Digital Techniques for Improved ΔΣ Data Conversion," IEEE CICC, pp. 183-190, May, 2002.
    • (2002) IEEE CICC , pp. 183-190
    • Silva, J.1    Wang, X.2    Kiss, P.3    Moon, U.-K.4    Temes, G.C.5
  • 7
    • 77954861622 scopus 로고    scopus 로고
    • Background DAC Error Estimation Using a Pseudo Random Noise Based Correlation Technique for Sigma-Delta Analog-to-Digital Converters
    • July
    • P. Witte and M. Ortmanns, "Background DAC Error Estimation Using a Pseudo Random Noise Based Correlation Technique for Sigma-Delta Analog-to-Digital Converters," IEEE TCAS-I, vol. 57, no. 7, pp. 1500-1512, July, 2010.
    • (2010) IEEE TCAS-I , vol.57 , Issue.7 , pp. 1500-1512
    • Witte, P.1    Ortmanns, M.2
  • 8
    • 51949086959 scopus 로고    scopus 로고
    • A 2.1 mW/3.2 mW Delay-Compensated GSM/WCDMA ΣΔ Analog-Digital Converter
    • June
    • M. Vadipour, C. Chen, C. Yazdi, et al., "A 2.1 mW/3.2 mW Delay-Compensated GSM/WCDMA ΣΔ Analog-Digital Converter," IEEE Symp. VLSI Circuits, pp. 180-181, June, 2008.
    • (2008) IEEE Symp. VLSI Circuits , pp. 180-181
    • Vadipour, M.1    Chen, C.2    Yazdi, C.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.