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A 20.7 mW Continuous-Time Delta-Sigma Modulator with 15 MHz Bandwidth and 70dB Dynamic Range
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A 0.13μm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-Based Integrator and Quantizer
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A 20MHz BW 68dB DR CT ΔΣ ADC Based on a Multi-Bit Time-Domain Quantizer and Feedback Element
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A 14b 20mW 640MHz CMOS CT DS ADC with 20MHz Signal Bandwidth and 12b ENOB
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Digital Techniques for Improved ΔΣ Data Conversion
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Background DAC Error Estimation Using a Pseudo Random Noise Based Correlation Technique for Sigma-Delta Analog-to-Digital Converters
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P. Witte and M. Ortmanns, "Background DAC Error Estimation Using a Pseudo Random Noise Based Correlation Technique for Sigma-Delta Analog-to-Digital Converters," IEEE TCAS-I, vol. 57, no. 7, pp. 1500-1512, July, 2010.
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A 2.1 mW/3.2 mW Delay-Compensated GSM/WCDMA ΣΔ Analog-Digital Converter
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June
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M. Vadipour, C. Chen, C. Yazdi, et al., "A 2.1 mW/3.2 mW Delay-Compensated GSM/WCDMA ΣΔ Analog-Digital Converter," IEEE Symp. VLSI Circuits, pp. 180-181, June, 2008.
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