A 0.08 mm2, 7mW time-encoding oversampling converter with 10 bits and 20MHz BW in 65nm CMOS

ESSCIRC 2010 - 36th European Solid State Circuits Conference

Volumn , Issue , 2010, Pages 430-433

  Prefasi, Enrique ^a   Paton, Susana ^a   Hernandez, Luis ^a   Gaggl, Richard ^b   Wiesbauer, Andreas ^c   Hauptmann, Joerg ^b  

^a UNIVERSIDAD CARLOS III DE MADRID   (Spain)

^b Lantiq A GmbH   (Austria)

^c INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN ISSUES; DIGITAL CMOS TECHNOLOGY; FIGURE OF MERIT; LOOP FILTER; MIXED-SIGNAL CIRCUITS; MULTI-BITS; NANO SCALE; OVER SAMPLING; POWER EFFICIENT; QUANTIZERS; REFERENCE BUFFERS; SELF-OSCILLATING; SIGNAL BANDWIDTH; SINGLE-BIT; SMALL AREA; TIME-RESOLUTION;

CMOS INTEGRATED CIRCUITS; ENCODING (SYMBOLS); MODULATORS;

INNOVATION;

EID: 78650369688     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2010.5619735     Document Type: Conference Paper

References (9)

1. E. Prefasi, L. Hernandez, S. Paton, A. Wiesbauer, R. Gaggl, E. Pun, "A 0.1mm2, Wide Bandwidth Continuous-Time ΣΔ ADC based on a Time Encoding Quantizer in 0.13μm CMOS," IEEE JSSC, vol. 44, no. 10, pp. 2745-2754, Oct. 2009
2. M. Park, and M. Perrott, "A 0.13μm CMOS 78dB SNDR 87mW 20MHz BW CT Delta-Sigma ADC with VCO-Based Integrator and Quantizer", ISSCC Dig. Tech. Papers, pp. 170-171, February 2009.
3. Yanfei Chen; S. Tsukamoto, T. Kuroda, "A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS," IEEE A-SSCC Dig. Tech. Papers, pp. 145-148, Nov. 2009.
4. M. Boulemnakher, et al., "A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS," ISSCC Dig. Tech. Papers, pp. 250-611, Feb. 2008.
5. L. Hernandez, E. Prefasi, "Analog to Digital Conversion using Noise Shaping and Time Encoding," IEEE TCAS I: Regular papers, vol. 55, no. 7, pp. 2026-2037, Aug. 2008.
6. S. Paton, et al., "A 70-mW 300-MHz CMOS Continuous-Time ΔΣ ADC with 15-MHz Bandwidth and 11 bits of Resolution," IEEE JSSC, vol. 39, no. 6, pp. 1056-1063, July 2004.
7. G. Mitteregger et al., "A 14b 20mW 640MHz CMOS CT Delta-Sigma ADC with 20MHz Signal Bandwidth and 12b ENOB", ISSCC Dig. Tech. Papers, pp. 62-63, February 2006.
8. V. Dhanasekaran, et al., "A 20MHz BW 68dB DR CT Delta-Sigma ADC Based on a Multi-Bit Time-Domain Quantizer and Feedback Element", ISSCC Dig. Tech. Papers, pp. 174-175, February 2009.
9. P. Crombez, et. al, "A Single Bit 6.8mW 10MHz Power-Optimized Continuous-Time ΔΣ with 67dB DR in 90nm CMOS," ESSCIRC Dig. Tech. Papers, pp. 336-339, Sep. 2009.