A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS

ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 336-339

  Crombez, Pieter ^a,b   Van Der Plas, Geert ^a   Steyaert, Michiel ^b   Craninckx, Jan ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; A/D CONVERTER; BROAD BAND WIRELESS SYSTEMS; CIRCUIT LEVELS; CONFIGURABLE; CONTINUOUS TIME; DIGITAL CMOS; HIGH DATA RATE; HIGH DYNAMIC RANGE; LOOP DELAY; LOW-POWER CONSUMPTION; OVERALL ENERGY EFFICIENCY; SIGNAL BANDWIDTH; SINGLE-BIT;

ANALOG TO DIGITAL CONVERSION; CONTINUOUS TIME SYSTEMS; ENERGY EFFICIENCY; GLOBAL OPTIMIZATION;

DIGITAL CIRCUITS;

EID: 72849146020     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2009.5326032     Document Type: Conference Paper

References (10)

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