메뉴 건너뛰기




Volumn 44, Issue 10, 2009, Pages 2745-2754

A 0.1 mm2, wide bandwidth continuous-time ∑δ ADC based on a time encoding quantizer in 0.13 μm CMOS

Author keywords

Analog to digital conversion; Continuous time filters; Low pass filters; Low voltage design; Pulse width modulation; Sigma delta modulation; Time encoding quantizer

Indexed keywords

ACTIVE AREA; CONTINUOUS TIME; CONTINUOUS TIME MODULATORS; CONTINUOUS-TIME FILTERS; DECIMATION FILTER; EFFECTIVE NUMBER OF BITS; ERROR SPECTRUM; FIGURE OF MERIT; LOW-VOLTAGE DESIGN; MULTI-BITS; OPERATING MODES; POWER EFFICIENT; QUANTIZATION ERRORS; QUANTIZERS; SELF-OSCILLATING; SIGMA-DELTA; SIGMA-DELTA MODULATION; SIGNAL BANDWIDTH; SINGLE FREQUENCY; SINGLE-BIT; THIRD ORDER; TIME DOMAIN; TIME ENCODING; TIME ENCODING QUANTIZER; WIDE BANDWIDTH;

EID: 70350584976     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2027550     Document Type: Article
Times cited : (34)

References (16)
  • 1
    • 33845630644 scopus 로고    scopus 로고
    • A 20-mW 640-MHz CMOS continuous-timeσδ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB
    • Dec.
    • G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, "A 20-mW 640-MHz CMOS continuous-timeσδ ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB," IEEE J. Solid-State Circuits, vol.41, no.12, pp. 2641-2649, Dec. 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.12 , pp. 2641-2649
    • Mitteregger, G.1    Ebner, C.2    Mechnig, S.3    Blon, T.4    Holuigue, C.5    Romani, E.6
  • 3
    • 10444270156 scopus 로고    scopus 로고
    • A continuous-timeσδ ADC with increased immunity to interferers
    • Dec.
    • K. Philips et al., "A continuous-timeσδ ADC with increased immunity to interferers," IEEE J. Solid-State Circuits, vol.39, no.12, pp. 2170-2178, Dec. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.12 , pp. 2170-2178
    • Philips, K.1
  • 4
    • 33644640551 scopus 로고    scopus 로고
    • Analysis and design of high-performance asynchronous sigma-delta modulators with a binary quantizer
    • Mar.
    • S. Ouzounov, E. Roza, J. A. Hegt, G. van der Weide, and A. H. M. van Roermund, "Analysis and design of high-performance asynchronous sigma-delta modulators with a binary quantizer," IEEE J. Solid-State Circuits, vol.41, no.3, pp. 588-596, Mar. 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.3 , pp. 588-596
    • Ouzounov, S.1    Roza, E.2    Hegt, J.A.3    Weide Der G.Van4    Van Roermund, A.H.M.5
  • 5
    • 7544229344 scopus 로고    scopus 로고
    • Perfect recovery and sensitivity analysis of time encoded bandlimited signals
    • Oct.
    • A. A. Lazar and L. T. Toth, "Perfect recovery and sensitivity analysis of time encoded bandlimited signals," IEEE Trans. Circuits Syst. I: Reg. Papers, vol.51, no.10, pp. 2060-2073, Oct. 2004.
    • (2004) IEEE Trans. Circuits Syst. I: Reg. Papers , vol.51 , Issue.10 , pp. 2060-2073
    • Lazar, A.A.1    Toth, L.T.2
  • 7
    • 44349123422 scopus 로고    scopus 로고
    • Continuous-time sigma-delta modulator with an embedded pulsewidth modulation
    • Apr.
    • F. Colodro, A. Torralba, and M. Laguna, "Continuous-time sigma-delta modulator with an embedded pulsewidth modulation," IEEE Trans. Circuits Syst. I: Reg. Papers, vol.55, no.4, pp. 775-785, Apr. 2008.
    • (2008) IEEE Trans. Circuits Syst. I: Reg. Papers , vol.55 , Issue.4 , pp. 775-785
    • Colodro, F.1    Torralba, A.2    Laguna, M.3
  • 8
    • 41549118015 scopus 로고    scopus 로고
    • A 12-Bit, 10-MHz bandwidth, continuous- timeσδ ADC with a 5-bit, 950-MS/s VCO-based quantizer
    • Apr.
    • M. Z. Straayer and M. H. Perrott, "A 12-Bit, 10-MHz bandwidth, continuous- timeσδ ADC with a 5-bit, 950-MS/s VCO-based quantizer," IEEE J. Solid-State Circuits, vol.43, no.4, pp. 805-814, Apr. 2008.
    • (2008) IEEE J. Solid-State Circuits , vol.43 , Issue.4 , pp. 805-814
    • Straayer, M.Z.1    Perrott, M.H.2
  • 9
    • 0030784975 scopus 로고    scopus 로고
    • Delta-sigma modulators using frequency-modulated intermediate values
    • Jan.
    • M. Hovin, A. Olsen, T. S. Lande, and C. Toumazou, "Delta-sigma modulators using frequency-modulated intermediate values," IEEE J. Solid-State Circuits, vol.32, no.1, pp. 13-112, Jan. 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , Issue.1 , pp. 13-112
    • Hovin, M.1    Olsen, A.2    Lande, T.S.3    Toumazou, C.4
  • 10
    • 50549094753 scopus 로고    scopus 로고
    • Analog to digital conversion using noise shaping and time encoding
    • Aug.
    • L. Hernandez and E. Prefasi, "Analog to digital conversion using noise shaping and time encoding," IEEE Trans. Circuits Syst. I, Reg. Papers, vol.55, no.8, pp. 2026-2037, Aug. 2008.
    • (2008) IEEE Trans. Circuits Syst. I, Reg. Papers , vol.55 , Issue.8 , pp. 2026-2037
    • Hernandez, L.1    Prefasi, E.2
  • 11
    • 29044435476 scopus 로고    scopus 로고
    • A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13- m CMOS
    • Dec.
    • L. Dorrer, F.Kuttner, P. Greco, P. Torta, and T. Hartig, "A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13- m CMOS," IEEE J. Solid-State Circuits, vol.40, no.12, pp. 2416-2427, Dec. 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.12 , pp. 2416-2427
    • Dorrer, L.1    Kuttner, F.2    Greco, P.3    Torta, P.4    Hartig, T.5
  • 13
    • 48349091329 scopus 로고    scopus 로고
    • Continuous time sigma delta modulator employing a novel comparator architecture
    • U. K. Vijay and A. Bharadwaj, "Continuous time sigma delta modulator employing a novel comparator architecture," in Proc. IEEE Conf. VLSI Design, 2007, pp. 919-924.
    • (2007) Proc. IEEE Conf. VLSI Design , pp. 919-924
    • Vijay, U.K.1    Bharadwaj, A.2
  • 14
    • 41549098703 scopus 로고    scopus 로고
    • A 77-dB dynamic range, 7.5-MHz hybrid continuous-time/discrete-time cascaded σδ modulator
    • Apr.
    • S. D. Kulchycki, R. Trofin, K. Vleugels, and B. A. Wooley, "A 77-dB dynamic range, 7.5-MHz hybrid continuous-time/discrete-time cascaded σδ modulator," IEEE J. Solid-State Circuits, vol.43, no.4, pp. 796-804, Apr. 2008.
    • (2008) IEEE J. Solid-State Circuits , vol.43 , Issue.4 , pp. 796-804
    • Kulchycki, S.D.1    Trofin, R.2    Vleugels, K.3    Wooley, B.A.4
  • 15
    • 38849180960 scopus 로고    scopus 로고
    • A 2.7-mW 2-MHz continuous-time σδ modulator with a hybrid active-passive loop filter
    • Feb.
    • T. Song, Z. Cao, and S. Yan, "A 2.7-mW 2-MHz continuous-time σδ modulator with a hybrid active-passive loop filter," IEEE J. Solid-State Circuits, vol.43, no.2, pp. 330-341, Feb. 2008.
    • (2008) IEEE J. Solid-State Circuits , vol.43 , Issue.2 , pp. 330-341
    • Song, T.1    Cao, Z.2    Yan, S.3
  • 16
    • 54249147523 scopus 로고    scopus 로고
    • 56 mW continuous-time quadrature cascaded ∑ δ modulator with 77 dB DR in a near zero-IF 20 MHZ band
    • Dec.
    • L. J. Breems, R. Rutten, R. H. M. van Veldhoven, and G. van derWeide, "56 mW continuous-time quadrature cascaded ∑ δ modulator with 77 dB DR in a near zero-IF 20 MHZ band," IEEE J. Solid-State Circuits, ol.42, no.12, pp. 2696-2705, Dec. 2007.
    • (2007) IEEE J. Solid-State Circuits , vol.42 , Issue.12 , pp. 2696-2705
    • Breems, L.J.1    Rutten, R.2    Van Veldhoven, R.H.M.3    Van Derweide, G.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.