A 0.13μm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based integrator and quantizer

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 170-172

  Park, Matt ^a   Perrott, Michael ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b SiTime Corporation   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349283738     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977362     Document Type: Conference Paper

References (5)

1. M. Hovin et al., "Delta-Sigma Modulators Using Frequency-Modulated Intermediate Values," IEEE J. Solid-State Circuits, vol.32, no.1, pp. 13-22, Jan. 1997.
2. M.Z. Straayer and M.H. Perrott, "A 12-bit 10-MHz Bandwidth, Continuous-Time Sigma-Delta ADC With a 5-bit, 950-MS/S VCO-Based Quantizer," IEEE J. Solid-State Circuits, vol.43, no.4, pp. 805-814, Apr. 2008.
3. S. Yan and E. Sanchez-Sinencio, "A Continuous-Time Modulator with 88-dB Dynamic Range and 1.1-MHz Signal Bandwidth," IEEE J. of Solid-State Circuits, vol.39, no.1, pp. 75-86, Jan. 2004.
4. G.Mitteregger et al., "A 20 mW 640-MHz CMOS Continuous-Time Sigma-Delta ADC with 20-MHz Signal Bandwidth, 80-dB Dynamic Range, and 12-bit ENOB," IEEE J. Solid- State Circuits, vol.41, no.12, pp. 2641-2649, Dec. 2006.
5. M. Miller, Multi-Bit Continuous-Time Sigma-Delta ADC, U.S. Patent 6, 700, 520, Mar. 2, 2004.