Investigation of nanowire line-edge roughness in gate-all-around silicon nanowire MOSFETs

IEEE Transactions on Electron Devices

Volumn 57, Issue 11, 2010, Pages 2864-2871

  Yu, Tao ^a   Wang, Runsheng ^a   Huang, Ru ^a   Chen, Jiang ^a   Zhuge, Jing ^a   Wang, Yangyuan ^a  

^a PEKING UNIVERSITY   (China)

Author keywords

Intrinsic parameter fluctuation; line edge roughness (LER); silicon nanowire MOSFET (SNWT); variability

Indexed keywords

CORRELATION LENGTHS; DEGREE OF FREEDOM; DEVICE PERFORMANCE; ELECTRICAL PARAMETER; GATE LENGTH; GATE-ALL-AROUND; INTRINSIC PARAMETER FLUCTUATION; LINE EDGE ROUGHNESS; MEAN VALUES; MOS-FET; NANOWIRE STRUCTURES; NON-GAUSSIAN DISTRIBUTION; PERFORMANCE DEGRADATION; PERFORMANCE VARIATIONS; RELATIVE IMPORTANCE; SILICON NANOWIRE MOSFETS; SOURCE/DRAIN EXTENSION REGIONS; STATISTICAL SIMULATION; TRADITIONAL DEVICES; TRANSVERSE DIRECTIONS; TWO DEGREES OF FREEDOM; VARIABILITY;

DEGRADATION; ELECTRIC WIRE; ELECTRON BEAM LITHOGRAPHY; MOSFET DEVICES; NANOWIRES; SEMICONDUCTING SILICON COMPOUNDS; SOIL STRUCTURE INTERACTIONS;

ROUGHNESS MEASUREMENT;

EID: 78049307956     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2065808     Document Type: Article

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