Experimental investigation and design optimization guidelines of characteristic variability in silicon nanowire CMOS technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Zhuge, Jing ^a,b   Wang, Runsheng ^a,b   Huang, Ru ^a,b   Zou, Jibin ^a,b   Huang, Xin ^a,b   Kim, D W ^c   Park, Donggun ^c   Zhang, Xing ^a,b   Wang, Yangyuan ^a,b  

^a PEKING UNIVERSITY   (China)

^b BEIJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS   (China)

^c SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; CONFINED GEOMETRIES; D-CHANNEL; DESIGN OPTIMIZATION; EXPERIMENTAL INVESTIGATIONS; GATE-ALL-AROUND; INTRINSIC CHANNEL; LINE EDGE ROUGHNESS; MEASURED RESULTS; METAL-GATE; ON-CURRENTS; OPERATING WINDOWS; PLANAR DEVICES; PROCESS VARIATION; QUANTUM EFFECTS; QUANTUM RESISTANCE; QUASI-BALLISTIC; RANDOM DOPANT FLUCTUATION; RANDOM TELEGRAPH SIGNAL NOISE; SILICON NANOWIRE MOSFETS; SILICON NANOWIRES; SRAM CELL;

CMOS INTEGRATED CIRCUITS; COMPUTER CRIME; ELECTRON DEVICES; GATES (TRANSISTOR); NANOWIRES; OPTIMIZATION; QUANTUM ELECTRONICS; SEMICONDUCTING SILICON COMPOUNDS; SMELTING; TELEGRAPH;

STATIC RANDOM ACCESS STORAGE;

EID: 77952414173     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424421     Document Type: Conference Paper

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