Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2009, Pages 94-95

  Ming, Li ^a   Kyoung, Hwan Yeo ^a   Sung, Dae Suk ^a   Yun, Young Yeoh ^a   Kim, Dong Won ^a   Tae, Young Chung ^a   Kyung, Seok Oh ^a   Lee, Won Seong ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

Ballistic transport; CMOS; Gate all around; Nanowire; Source drain parasitic resistance

Indexed keywords

BALLISTIC TRANSPORT; CMOS; GATE OXIDE THICKNESS; GATE-ALL-AROUND; NANOWIRE TRANSISTORS; OFF-LEAKAGE CURRENT; ON STATE CURRENT; PARASITIC RESISTANCES; SI SUBSTRATES; SILICON NANOWIRE FIELD-EFFECT TRANSISTORS; SILICON NANOWIRES; SOURCE-DRAIN PARASITIC RESISTANCE;

BALLISTICS; FIELD EFFECT TRANSISTORS; GALLIUM ALLOYS; LEAKAGE CURRENTS; TRANSPORT PROPERTIES;

NANOWIRES;

EID: 71049178703     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. S.D.Suk et al., IEDM Tech. Dig., p.717, 2005.
2. K.H.Yeo et al., IEDM Tech. Dig., p.539, 2006.
3. F.L.Yang et al., VLSI Tech. Symp., p.196, 2004.
4. Y. Jiang et al., VLSI Tech. Symp., p.34, 2008.
5. S.D.Suk et al., IEDM Tech. Dig., p.891, 2007.
6. Y. Taur, T.H. Ning, Fund. Of Modern VLSI Devices, p.215, 1998