Gate line edge roughness model for estimation of FinFET performance variability

IEEE Transactions on Electron Devices

Volumn 56, Issue 12, 2009, Pages 3055-3063

  Patel, Kedar ^a,b   Liu, Tsu Jae King ^c   Spanos, Costas J ^c  

^a SanDisk Corporation   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Double gate (DG); FinFET; Intrinsic parameter fluctuation; Line edge roughness (LER); Variability

Indexed keywords

DOUBLE GATE; FINFET; INTRINSIC PARAMETER FLUCTUATION; LINE EDGE ROUGHNESS; VARIABILITY;

INTEGRATED CIRCUITS; MONTE CARLO METHODS; MOSFET DEVICES;

ROUGHNESS MEASUREMENT;

EID: 78650145573     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2032605     Document Type: Article

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