Layout optimizations for double patterning lithography

ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Volumn , Issue , 2009, Pages 726-729

  Pan, David Z ^a   Yang, Jae Seok ^a   Yuan, Kun ^a   Cho, Minsik ^a,b   Ban, Yongchan ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Decomposition; Detailed routing; Double patterning lithography; Layout optimization; Redundant via

Indexed keywords

DETAILED ROUTING; DOUBLE PATTERNING; DOUBLE PATTERNING LITHOGRAPHY; LAYOUT OPTIMIZATION; REDUNDANT VIA;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS;

LITHOGRAPHY;

EID: 77949408930     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASICON.2009.5351308     Document Type: Conference Paper

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