SCOPUS 정보 검색 플랫폼

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2009, Pages 107-114

Double patterning layout decomposition for simultaneous conflict and stitch minimization

(3) Yuan, Kun a Yang, Jae Seok a Pan, David Z a

a UNIVERSITY OF TEXAS AT AUSTIN (United States)

Author keywords

Double patterning lithography; Integer linear programming; Layout decompositio

Indexed keywords

COMPLEX PATTERN; DOUBLE PATTERNING; DOUBLE PATTERNING LITHOGRAPHY; GRID LAYOUT; INDEPENDENT COMPONENTS; INTEGER LINEAR PROGRAMMING; LAYOUT DECOMPOSITIO; LAYOUT DECOMPOSITION; LAYOUT PATTERNS; MANUFACTURING COST; MINIMUM DISTANCE; OVERLAY ERRORS; PROPER COLORING; RUNTIMES; TWO-PHASE DECOMPOSITION; YIELD LOSS;

ALGORITHMS; COLORING; DYNAMIC PROGRAMMING; LINEAR PROGRAMMING; LINEARIZATION; OPTIMIZATION;

INTEGER PROGRAMMING;

EID: 70349152186 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1145/1514932.1514958 Document Type: Conference Paper

Times cited : (62)

References (9)

1
- 41449114142
- Double patterning lithography: The bridge between low kl arf and euv
- Feb
- Micrea Dusa, Jo Finders, and Stephen Hsu. Double patterning lithography: The bridge between low kl arf and euv. In Microlithography World, Feb 2008.
- (2008) Microlithography World
- Dusa, M.¹ Finders, J.² Hsu, S.³

2
- 35148841978
- Double pattern EDA solutions for 32nm HP and beyond
- George E. Bailey, Alexander Tritchkov, Jea-Woo Park, Le Hong, Vincent Wiaux, Eric Hendrickx, Staf Verhaegen, Peng Xie, and Janko Versluijs. Double pattern EDA solutions for 32nm HP and beyond. In Proc. SPIE 6521, 2007.
- (2007) Proc. SPIE 6521
- Bailey, G.E.¹ Tritchkov, A.² Park, J.-W.³ Hong, L.⁴ Wiaux, V.⁵ Hendrickx, E.⁶ Verhaegen, S.⁷ Xie, P.⁸ Versluijs, J.⁹

3
- 45449095473
- Split and design guidelines for double patterning
- V. Wiaux, S. Verhaegen, S. Cheng, F. Iwamoto, P. Jaenen, M. Maenhoudt, T. Matsuda, S. Postnikov, and G. Vandenberghe. Split and design guidelines for double patterning. In Proc. of SPIE, volume 6924, 2008.
- (2008) Proc. of SPIE , vol.6924
- Wiaux, V.¹ Verhaegen, S.² Cheng, S.³ Iwamoto, F.⁴ Jaenen, P.⁵ Maenhoudt, M.⁶ Matsuda, T.⁷ Postnikov, S.⁸ Vandenberghe, G.⁹

4
- 39549114053
- Key Directions and a Roadmap for Electrical Design for Manufacturability
- A. B. Kahng. Key Directions and a Roadmap for Electrical Design for Manufacturability. In Proc. European Solid-State Circuits Conf, 2007.
- (2007) Proc. European Solid-State Circuits Conf
- Kahng, A.B.¹

5
- 35148840123
- Double patterning design split implementation and validation for the 32nm node
- M. Drapeau, V. Wiaux, E. Hendrickx, S. Verhaegen, and T. Machida. Double patterning design split implementation and validation for the 32nm node. In Proc. of SPIE, volume 6521, 2007.
- (2007) Proc. of SPIE , vol.6521
- Drapeau, M.¹ Wiaux, V.² Hendrickx, E.³ Verhaegen, S.⁴ Machida, T.⁵

6
- 45449093398
- Tsann-Bim Chiou, Robert Socha, Hong Chen, Luoqi Chen, Stephen Hsu, Peter Nikolsky, Anton van Oosten, and Alek C. Chen. Development of layout split algorithms and printability evaluation for double patterning technology. In Proc. of SPIE, March 2008.
- Tsann-Bim Chiou, Robert Socha, Hong Chen, Luoqi Chen, Stephen Hsu, Peter Nikolsky, Anton van Oosten, and Alek C. Chen. Development of layout split algorithms and printability evaluation for double patterning technology. In Proc. of SPIE, March 2008.

7
- 57849119643
- Layout decomposition for double patterning lithography
- November
- Andrew B. Kahng, Chul-Hong Park, Xu Xu, and Hailong Yao. Layout decomposition for double patterning lithography. In Proc. Int. Gonf. on Computer Aided Design, November 2008.
- (2008) Proc. Int. Gonf. on Computer Aided Design
- Kahng, A.B.¹ Park, C.-H.² Xu, X.³ Yao, H.⁴

8
- 70349118349
- http://www.gnu.org/software/glpk/glpk.html.

9
- 70349104835
- http://glaros.dtc.umn.edu/gkhome/views/metis.

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.