Sources of overlay error in double patterning integration schemes

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6922, Issue , 2008, Pages

  Laidler, David ^a   Leray, Philippe ^a   D'Havé, Koen ^a   Cheng, Shaunee ^a  

^a IMEC   (Belgium)

Author keywords

Alignment strategy; Design split; DPT (double patterning technology); Overlay error; Residual

Indexed keywords

DOUBLE PATTERNING; FOCUS OF ATTENTION; INTEGRATION SCHEME; INTEGRATION STRATEGY; KEY PARTS; NON-LINEAR; ON-WAFER; OVERLAY ERRORS; PROCESS IMPACT; PROCESS STEPS; RESIDUAL; WAFER DEFORMATION;

ALIGNMENT; DEFORMATION; INTEGRATION; UNITS OF MEASUREMENT;

PROCESS CONTROL;

EID: 57849158474     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.773575     Document Type: Conference Paper

References (5)

1. M. Dusa, et. al., "Pitch Doubling Through Dual Patterning Lithography Challenges in Integration and Litho Budgets", Proc. SPIE (2007), 6520-16.
2. W. Arnold, M. Dusa, "Manufacturing Challenges in Double Patterning Lithography", ISSM, MC-233, Sept. 2006.
3. Y. Hwang, et. al., "Improvement of Alignment and Overlay Accuracy on Amorphous Carbon Layers", Proc. SPIE (2006), 6152-73.
4. D. Laidler, "Identifying Sources of Overlay Error in FinFET Technology", Proc. SPIE (2005), 5752-10.
5. C.P. Ausschnitt, J. Morillo, R.J. Yerdon, "Combined layer-to-layer and within layer overlay control, " Proc. SPIE (2002), 4689-28.