Double-patterning-friendly OPC

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7274, Issue , 2009, Pages

  Li, Xiaohai ^a   Luk Pat, Gerry ^a   Cork, Chris ^a   Barnes, Levi ^a   Lucas, Kevin ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL LAYER; DESIGN LAYOUT; DOUBLE PATTERNING; ETCH BIAS; ETCH PROCESS; LAYOUT DECOMPOSITION; MASK LAYOUT; OPTICAL PROXIMITY CORRECTIONS; ORIGINAL DESIGN; OVERLAP REGION; PATTERNING LAYERS; PROCESS INTERACTION; PROCESS VARIABLES; SINGLE EXPOSURE; TEST PATTERN;

ELECTRON BEAM LITHOGRAPHY;

TITRATION;

EID: 65849338169     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.815175     Document Type: Conference Paper

References (5)

1. M. Drapeau, et al., "Double Patterning Design Split Implementation and Validation for the 32nm Node", Proc. SPIE, Vol.6521, 652109 (2007).
2. G. Luk-Pat, et al., "Printability Verification for Double-Patterning Technology", Proc. SPIE, Vol.7122, 71220Q (2008).
3. K. Lucas, et al., "Interactions of Double Patterning Technology with Wafer Processing, OPC and Design Flows", Proc. SPIE, Vol.6924, 692403 (2008).
4. R. Lugg, et al., "Full-chip Process Window Aware OPC Capability Assessment", Proc. SPIE, Vol.6730, 67302U (2007).
5. D. Laidler, et al., "Sources of Overlay Error in Double Patterning Integration Schemes", Proc. SPIE, Vol.6922, 69221E (2008).