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Volumn , Issue , 2008, Pages 465-472

Layout decomposition for double patterning lithography

Author keywords

[No Author keywords available]

Indexed keywords

45NM TECHNOLOGIES; COLOR SPACINGS; CYCLE DETECTIONS; DESIGN RULES; DOUBLE PATTERNING; GRAPH CONSTRUCTIONS; LAYOUT DECOMPOSITIONS; LAYOUT FEATURES; PROCESS NODES; SPLITTING PROCESSES;

EID: 57849119643     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681616     Document Type: Conference Paper
Times cited : (138)

References (19)
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    • G. Capetti et al., "Sub k1 = 0.25 Lithography with Double Patterning Technique for 45nm Technology Node Flash Memory Devices at 193nm", Proc. SPIE Conf. on Optical Microlithography, 2007, pp. 65202K-1 - 65202K-12.
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    • Capetti, G.1
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    • Fast and Efficient Phase Conflict Detection and Correction in Standard-Cell Layouts
    • C. Chiang, A. B. Kahng, S. Sinha and X. Xu, "Fast and Efficient Phase Conflict Detection and Correction in Standard-Cell Layouts", Proc. ICCAD, 2005, pp. 149-156.
    • (2005) Proc. ICCAD , pp. 149-156
    • Chiang, C.1    Kahng, A.B.2    Sinha, S.3    Xu, X.4
  • 10
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    • Pitch Doubling Through Dual-Patterning Lithography Challenges in Integration and Litho Budgets
    • 65200G-10
    • M. Dusa et al., "Pitch Doubling Through Dual-Patterning Lithography Challenges in Integration and Litho Budgets", Proc. SPIE Conf. on Optical Microlithography, 2007. pp. 65200G-1 - 65200G-10.
    • (2007) Proc. SPIE Conf. on Optical Microlithography
    • Dusa, M.1
  • 11
    • 41449114142 scopus 로고    scopus 로고
    • Double Patterning Lithography: The Bridge Between Low kl ArF and EUV
    • Feb
    • J. Finders, M. Dusa and S. Hsu. "Double Patterning Lithography: The Bridge Between Low kl ArF and EUV", Microlithography World, Feb. 2008.
    • (2008) Microlithography World
    • Finders, J.1    Dusa, M.2    Hsu, S.3
  • 12
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    • http://en.wikipedia.org/wiki/Hardmask.
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    • Issues and Challenges of Double Patterning Lithography in DRAM
    • 65200H-7
    • S.-M. Kim et al., "Issues and Challenges of Double Patterning Lithography in DRAM", Proc. SPIE Conf. on Optical Microlithography, 2006, pp. 65200H-1 - 65200H-7.
    • (2006) Proc. SPIE Conf. on Optical Microlithography
    • Kim, S.-M.1
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    • Positive and Negative Tone Double Patterning Lithography for 50nm Flash Memory
    • 615410-8
    • C. Lim et al., "Positive and Negative Tone Double Patterning Lithography for 50nm Flash Memory", Proc. SPIE Conf. on Optical Microlithography. 2006, pp. 615410-1 - 615410-8.
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    • Lim, C.1
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    • W.-Y. Jung et al., Patterning With Spacer for Expanding the Resolution Limit of Current Lithography Tool, Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing, 6125 pp. 61561J-1 - 61561J-9, 2006.
    • W.-Y. Jung et al., "Patterning With Spacer for Expanding the Resolution Limit of Current Lithography Tool", Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing, vol. 6125 pp. 61561J-1 - 61561J-9, 2006.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.