SCOPUS 정보 검색 플랫폼

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2008, Pages 488-493

Overlay aware interconnect and timing variation modeling for double patterning technology

(2) Yang, Jae Seok a Pan, David Z a

a UNIVERSITY OF TEXAS AT AUSTIN (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COUPLING CAPACITANCES; DELAY VARIATIONS; DOUBLE PATTERNING; INTER-CONNECTS; LAYOUT DECOMPOSITIONS; LITHOGRAPHY PROCESSES; PARALLEL PATTERNS; SPACING VARIATIONS; TIMING VARIATIONS;

CAPACITANCE; COMPUTER AIDED DESIGN; LITHOGRAPHY; METAL RECOVERY; TITRATION;

TIME MEASUREMENT;

EID: 57849138456 PISSN: 10923152 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ICCAD.2008.4681619 Document Type: Conference Paper

Times cited : (32)

References (9)

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2
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3
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- Sources of Overlay Error in Double Patterning Integration Schemes
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- Laidler, D.¹ Leray, P.² D'have, K.³ Cheng, S.⁴

4
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- (2008) Pmc. SPIE , vol.6924
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5
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6
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