Double patterning lithography friendly detailed routing with redundant via consideration

Proceedings - Design Automation Conference

Volumn , Issue , 2009, Pages 63-66

  Kun, Yuan ^a   Lu, Katrina ^a   Pan, David Z ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

Detailed routing; Double patterning; Redundant via

Indexed keywords

2D PATTERNS; DETAILED ROUTING; DOUBLE PATTERNING; HIGH-QUALITY SOLUTIONS; INSERTION RATES; LAYOUT DECOMPOSITION; METAL LAYER; REDUNDANT VIA; REDUNDANT VIA INSERTION; YIELD IMPROVEMENT;

COLORING; COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS;

ROUTING ALGORITHMS;

EID: 70350706638     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Andrew B. Kahng et al. Layout decomposition for double patterning lithography. In Proc. of ICCAD, November 2008.
2. Kun Yuan et al. Double patterning layout decomposition for simultaneous conflict and stitch minimization. In Proc. of ISPD, March 2009.
3. Minsik Cho et al. Double patterning technology friendly detailed routing. In Proc. of ICCAD, November 2008.
4. Huang-Yu Chen et al. Novel Full-Chip Gridless Routing Considering Double-Via Insertion. In Proc. of DAC, Jul 2006.
5. Kuang-Yao Lee et al. Optimal post-routing redundant via insertion. In Proc. of ISPD, April 2008.
6. Mircea Dusa et al. Pitch doubling through dual-patterning lithography challenges in integration and litho budgets. In Proc. of SPIE, March 2007.
7. G. Xu et al. Redundant-Via Enhanced Maze Routing for Yield Improvement. In Proc. Asia and South Pacific Design Automation Conf., Jan 2005.
8. http://www.gnu.org/software/glpk/glpk.html/.