Interactions of double patterning technology with wafer processing, OPC and design flows

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6924, Issue , 2008, Pages

  Lucas, Kevin ^a   Cork, Chris ^b   Miloslavsky, Alex ^a   Luk Pat, Gerry ^a   Barnes, Levi ^a   Hapli, John ^a   Lewellen, John ^a   Rollins, Greg ^a   Wiaux, Vincent ^c   Verhaegen, Staf ^c  

^a SYNOPSYS INC   (United States)

^b Synopsys SARL   (France)

^c IMEC   (Belgium)

Author keywords

Design rules; Double patterning technology (DPT); Place route; Standard cell design

Indexed keywords

ARCHITECTURAL DESIGN; COMPUTER NETWORKS; DATA STORAGE EQUIPMENT; FLASH MEMORY; FLOW INTERACTIONS; LITHOGRAPHY; LOGIC DEVICES; PROCESS DESIGN; PROCESS ENGINEERING; RHENIUM; TECHNOLOGY; TITRATION;

(ALGORITHMIC) COMPLEXITY; (E ,3E) PROCESS; (P ,K)-COLORING; (R ,S)-SYMMETRIC; (T ,S)-SPLITTING; 193-NM LITHOGRAPHY; CIRCUIT AREA; CRITICAL SOFTWARE; DESIGN FLOWS; DESIGN INTENT; DOUBLE EXPOSURE; DOUBLE PATTERNING; INDIVIDUAL (PSS 544-7); MASK SYNTHESIS; MASKING LAYERS; OPTICAL MICRO LITHOGRAPHY; ORIGINAL DESIGN; PATTERNING LAYERS; PHYSICAL DESIGNS; SYNTHESIS (OF CHIRAL IONIC LIQUIDS); WAFER PROCESSING;

SOFTWARE DESIGN;

EID: 45449119111     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.778267     Document Type: Conference Paper

References (3)

1. Martin Drapeau, et al. Patterning Design Split Implementation and Validation for the 32nm Node. Proc. of SPIE, Vol. 6521, 2007.
2. George Bailey, et al, Double pattern EDA solutions for 32nm HP and beyond. Proc. of SPIE, Vol. 6521, 2007.
3. D. G. Piercea, P. G. Brusius. J. Microelectronics and Reliability, Volume 37, Issue 7, July 1997, Pp 1053-1072.