Double pattern EDA solutions for 32nm HP and beyond

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6521, Issue , 2007, Pages

  Bailey, George E ^a   Tritchkov, Alexander ^a   Park, Jea Woo ^a   Hong, Le ^a   Wiaux, Vincent ^b   Hendrickx, Eric ^b   Verhaegen, Staf ^b   Xie, Peng ^a   Versluijs, Janko ^b  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b IMEC   (Belgium)

Author keywords

Double exposure; Double patterning; EDA; Hyper NA; OPC

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; IMAGING SYSTEMS; INTEGRATED CIRCUIT LAYOUT; INTEROPERABILITY; LOGIC CIRCUITS; OPTIMIZATION;

DOUBLE EXPOSURE; DOUBLE PATTERNING; HYPER-NA;

LITHOGRAPHY;

EID: 35148841978     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.712773     Document Type: Conference Paper

References (10)

1. M. Maenhoudt, et al., "Double Patterning Scheme for Sub-0.25 k1 Single Damascene Structure at NA=0.75, λ= 193nm," Proceedings of SPIE, vol. 5754, pp 1508-1518, 2004.
2. Lars Liebmann, "Layout Methodology Impact of Resolution Enhancement Technique," Electronic Design Process, Monterey, CA, 2003.
3. Jungchul Park, et al., "Application Challenges with Double Patterning Technology beyond 45nm," Proceedings of SPIE, vol. 6349, pp 634922-33, 2006.
4. V. Wiaux, et al., "193nm Immersion Lithography towards 32nm hp using Double Patterning", 3rd International Symposium on Immersion Lithography, Kyoto, 2-5 October, 2006.
5. M. Op de Beeck, et al., "Manufacturability issues with double patterning for 50-nm half-pitch single damascene applications using Relacs shrink and corresponding OPC", Proceedings of SPIE, vol. 6520, 2007.
6. L. Hong, T. Brist, P. LaCour, J. Sturtevant, M. Niehoff, Phillip Niedermaier, "Impact of process variance on 65nm across-chip linewidth variation," Proceedings of SPIE, vol. 6156, pp 61560Q1-9, 2006.
7. K. Lucas, K. Patterson, R. Boone, C. Miramond, A. Borjon, J. Belledent, O. Toublan, J. Entradas, Y. Trouiller, "Reticle enhancement verification for 65nm and 45nm nodes," Proceedings of SPIE, vol. 6156, pp 61560Q1-9, 2006.
8. T. Brist, S. Schulze, "Illumination optimization effects on OPC and MDP," Proceedings of SPIE, vol. 5754, pp 1179-1189, 2004.
9. T. Brist, G. Bailey, "Effective multicutline QUASAR illumination optimization for SRAM and logic," Proceedings of SPIE, vol. 5042, pp 153-159, 2003.
10. T. Brist, G. Bailey, A. Drozdov, A. Torres, A. Estroff, E. Hendrix, "Source polarization and OPC effects on illumination optimization," Proceedings of SPIE, vol. 5992, pp 599232-1/9, 2005.