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1
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77949352024
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Alignment system and process optimization for improvement of double patterning overlay
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Won-kwang Ma, Jung-hyun Kang, Chang-moon Lim, HyeongSoo Kim, and Seung-chan Moon, "Alignment system and process optimization for improvement of double patterning overlay," Proc. SPIE 6922, 69222T (2008).
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Won-kwang, M.1
Kang, J.-H.2
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Kim, H.4
Moon, S.-C.5
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2
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45449085022
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Double patterning in lithography for 65nm node with oxidation process
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Eunsoo Jeong, Jeahee Kim, Kwangsun Choi, Minkon Lee, Doosung Lee, Myungsoo Kim and Chansik Park, "Double patterning in lithography for 65nm node with oxidation process," Proc. SPIE 6924, 692424 (2008).
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Jeong, E.1
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Lee, M.4
Lee, D.5
Kim, M.6
Park, C.7
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3
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45449117473
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32 nm logic patterning options with immersion lithography
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K. Lai, S. Burns, S. Halle, L. Zhuang, M. Colburn, S. Allen, C. Babcock, Z. Baum, M. Burkhardt, V. Dai, D. Dunn, E. Geiss, H. Haffner, G. Han, P. Lawson, S. Mansfield, J. Meiring, B. Morgenfeld, C. Tabery, Y. Zou, C. Sarma, L. Tsou, W. Yan, H. Zhuang, D. Gil, and D. Medeiros,"32 NM LOGIC PATTERNING OPTIONS WITH IMMERSION LITHOGRAPHY," Proc. SPIE 6924, 69243C (2008).
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Lai, K.1
Burns, S.2
Halle, S.3
Zhuang, L.4
Colburn, M.5
Allen, S.6
Babcock, C.7
Baum, Z.8
Burkhardt, M.9
Dai, V.10
Dunn, D.11
Geiss, E.12
Haffner, H.13
Han, G.14
Lawson, P.15
Mansfield, S.16
Meiring, J.17
Morgenfeld, B.18
Tabery, C.19
Zou, Y.20
Sarma, C.21
Tsou, L.22
Yan, W.23
Zhuang, H.24
Gil, D.25
Medeiros, D.26
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4
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65849422556
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Accurate in-resolution level overlay metrology for multi patterning lithography techniques
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Ilan Englard, Rich Piech, Claudio Masia, Noam Hillel, Liraz Gershtein, Dana Sofer, Ram Peltinov, and Ofer Adan, "Accurate in-resolution level overlay metrology for multi patterning lithography techniques," Proc. SPIE 6922, 69221D (2008).
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Englard, I.1
Piech, R.2
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Gershtein, L.5
Sofer, D.6
Peltinov, R.7
Adan, O.8
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5
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57349174494
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Rigorous physical modeling of a materials-based frequency doubling lithography process
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Stewart A. Robertson, John J. Biafore, Trey Graves and Mark D. Smith, "Rigorous physical modeling of a materials-based frequency doubling lithography process," Proc. SPIE 6923, 692301 (2008).
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Proc. SPIE
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Robertson, S.A.1
Biafore, J.J.2
Graves, T.3
Smith, M.D.4
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6
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57849158474
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Sources of overlay error in double patterning integration schemes
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David Laidler, Philippe Leray, Koen D'havé and Shaunee Cheng, "Sources of Overlay Error in Double Patterning Integration Schemes," Proc. SPIE 6922, 69221E (2008).
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Laidler, D.1
Philippe Leray, K.D.2
Cheng, S.3
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7
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45449106995
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Towards 3nm overlay and critical dimension uniformity: An integrated error budget for double patterning lithography
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William H Arnold, " Towards 3nm overlay and critical dimension uniformity: an integrated error budget for double patterning lithography," Proc. SPIE 6924, 692413 (2008).
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Arnold, W.H.1
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8
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45449095902
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45nm and 32nm half-pitch patterning with 193nm dry lithography and double patterning
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Huixiong Dai, Chris Bencher, Yongmei Chen, Hyungje Woo, Chris Ngai, and Xumou Xu, "45nm and 32nm Half-Pitch Patterning with 193nm Dry Lithography and Double Patterning," Proc. SPIE 6924, 692421 (2008).
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Dai, H.1
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Chen, Y.3
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Ngai, C.5
Xu, M.6
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9
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45449112590
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Double patterning for 32nm and below: An update
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Jo Finders, Mircea Dusa, Bert Vleeming, Henry Megens, Birgitt Hepp, Mireille Maenhoudt, Shaunee Cheng and Tom Vandeweyer, "Double patterning for 32nm and below: an update," Proc. SPIE 6924, 692408 (2008).
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Finders, J.1
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Hepp, B.5
Maenhoudt, M.6
Cheng, S.7
Vandeweyer, T.8
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10
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45449094587
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Precise CD Control Techniques for Double Patterning Sidewall Transfer
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Eiichi Nishimura, Masato Kushibiki and Koichi Yatsuda, "Precise CD Control Techniques for Double Patterning Sidewall Transfer," Proc. SPIE 6924, 692425 (2008).
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Nishimura, E.1
Kushibiki, M.2
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11
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45449086042
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22nm half-pitch patterning by CVD spacer self alignment double patterning (SADP)
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Christopher Bencher, Yongmei Chen, Huixiong Dai, Warren Montgomery and Lior Huli, "22nm Half-Pitch Patterning by CVD Spacer Self Alignment Double Patterning (SADP)," Proc. SPIE 6924, 69244E (2008).
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Bencher, C.1
Chen, Y.2
Dai, H.3
Montgomery, W.4
Huli, L.5
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12
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45449095901
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Double patterning overlay and CD budget for 32 nm technology node
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Umberto lessi, Sara Loi, Antonio Salerno, Pierluigi Rigolli, Elio De Chiara, Catia Turco, Roberto Colombo, Marco Polli, and Antonio Mani, "Double Patterning Overlay and CD budget for 32 nm technology node," Proc. SPIE 6924, 692421 (2008).
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Lessi, U.1
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De Chiara, E.5
Turco, C.6
Colombo, R.7
Polli, M.8
Mani, A.9
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13
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62449140626
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Spacer double patterning technique for sub-40nm DRAM manufacturing process development
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Weicheng Shiu, William Ma, Hong Wen Lee, Jan Shiun Wu, Yi Min Tseng, Kevin Tsai, Chun Te Liao, Aaron Wang, Alan Yau, Yi Ren Lin, Yu Lung Chen, Troy Wang, Wen Bin Wu, and Chiang Lin Shih, "Spacer double patterning technique for sub-40nm DRAM manufacturing process development," Proc. SPIE 7140, 71403Y (2008).
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Shiu, W.1
William, M.2
Lee, H.W.3
Wu, J.S.4
Tseng, Y.M.5
Tsai, K.6
Liao, C.T.7
Wang, A.8
Yau, A.9
Lin, Y.R.10
Chen, Y.L.11
Wang, T.12
Wu, W.B.13
Shih, C.L.14
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