Split, overlap/ stitching and process design for double patterning considering local reflectivity variation by using rigorous 3D wafer-topography/ lithography simulation

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7274, Issue , 2009, Pages

  Kamohara, Itaru ^a   Schmoeller, Thomas ^b  

^a Synopsys Japan   (Japan)

^b Synopsys GmbH   (Germany)

Author keywords

Double patterning; NILS; Process window; Simulation; Wafer topography

Indexed keywords

DOUBLE PATTERNING; NILS; PROCESS WINDOW; SIMULATION; WAFER-TOPOGRAPHY;

DESIGN; DYNAMIC POSITIONING; ENGINEERING GEOLOGY; IMAGE RECORDING; MAGNETIC FIELDS; OPTIMIZATION; PERCOLATION (SOLID STATE); PROCESS DESIGN; REFLECTION; THREE DIMENSIONAL; WINDOWS;

LITHOGRAPHY;

EID: 65849275915     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.813976     Document Type: Conference Paper

References (8)

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4. Joachim Siebert, et al., "Analysis of topography effects on lithographic performance in double-patterning applications", Proc. SPIE 7274-21, Optical Microlithography XXII (2009).
5. Christopher Bencher, et al., "22nm Half-Pitch Patterning by CVD Spacer Self-Aligned Double Patterning", Proc. SPIE 69244E, Optical Microlithography XXI (2008).
6. Andreas Erdmann, et al., "Rigorous simulation of exposure over nonplanar wafers", Proc. SPIE 5040-101 (2003).
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8. IC WorkBench Plus, Synopsys, Inc. http://www.svnopsvs.com.