Leakage-delay tradeoff in finfet logic circuits: A comparative analysis with bulk technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 2, 2010, Pages 232-245

  Agostinelli, Matteo ^a   Alioto, Massimo ^b   Esseni, David ^c   Selmi, Luca ^c  

^a UNIVERSITY OF KLAGENFURT   (Austria)

^b UNIVERSITY OF SIENA   (Italy)

^c UNIVERSITY OF UDINE   (Italy)

Author keywords

Back biasing; Double gate MOSFETs; Fin FETs (FinFETs); Independent gates; Leakage reduction; Stack effect

Indexed keywords

BULK MOSFET; BULK TECHNOLOGIES; CIRCUIT LEVELS; COMPARATIVE ANALYSIS; DOUBLE-GATE MOSFETS; DYNAMIC PERFORMANCE; ENERGY EFFICIENT; FIGURES OF MERITS; FINFETS; FULL ADDERS; GATE CIRCUIT; LEAKAGE REDUCTION; LOW STAND-BY POWER; RING OSCILLATOR; STACK EFFECT; STANDBY POWER;

ADDERS; DELAY CIRCUITS; ELECTRIC CONVERTERS; ELECTRIC POWER UTILIZATION; FINS (HEAT EXCHANGE); LOGIC CIRCUITS; MESFET DEVICES; OSCILLATORS (ELECTRONIC); SWITCHING CIRCUITS;

MOSFET DEVICES;

EID: 75549083819     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2009633     Document Type: Article

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