Cointegration of high-performance tied-gate three-terminal FinFETs and variable threshold-voltage independent-gate four-terminal FinFETs with asymmetric gate-oxide thicknesses

IEEE Electron Device Letters

Volumn 28, Issue 6, 2007, Pages 517-519

  Liu, Yongxun ^a   Matsukawa, Takashi ^a   Endo, Kazuhiko ^a   Masahara, Meishoku ^a   O'uchi, Shin Ichi ^a   Ishii, Kenichi ^a   Yamauchi, Hiromi ^a   Tsukada, Junichi ^a   Ishikawa, Yuki ^a   Suzuki, Eiichi ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

Asymmetric gate oxide thicknesses; Cointegration; Double gate MOSFET; FinFET; Independent gate FinFET; Threshold voltage control; TiN gate

Indexed keywords

INTEGRATED CIRCUITS; INTEGRATION; REACTIVE SPUTTERING; THRESHOLD VOLTAGE; TITANIUM NITRIDE; VOLTAGE CONTROL;

ASYMMETRIC GATE-OXIDE THICKNESSES; COINTEGRATION; GATE-OXIDE FORMATION;

GATES (TRANSISTOR);

EID: 34249803816     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.896898     Document Type: Article

References (9)

1. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "FinFET - A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
2. Y. X. Liu, K. Ishii, T. Tsutsumi,M.Masahara, and E. Suzuki, "Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching," IEEE Electron Device Lett. vol. 24, no. 7, pp. 484-486, Jul. 2003.
3. D. M. Fried, J. S. Duster, and K. T. Kornegay, "Improved independent gate n-type FinFET fabrication and characterization," IEEE Electron Device Lett., vol. 24, no. 9, pp. 592-594, Sep. 2003.
4. Y. X. Liu, M. Masahara, K. Ishii, T. Tsutsumi, T. Sekigawa, H. Takashima, H. Yamauchi, and E. Suzuki, "Flexible threshold voltage FinFETs with independent double gates and an ideal rectangular cross-section Si-fin channel," in IEDM. Tech. Dig., 2003, pp. 986-988.
5. L. Mathew, Y. Du, S. Kalpat, M. Sadd, M. Zavala, T. Stephens, R. Mora, R. Rai, S. Becker, C. Parker, D. Sing, R. Shimer, J. Sanez, A. V.-Y. Thean, L. Prabhu, M. Moosa, B.-Y. Nguyen, J. Mogab, G. O. Workman, A. Vandooren, Z. Shi, M. M. Chowdhury, W. Zhang, and J. G. Fossum, "Multiple independent gate field effect transistor (MIGFET -multi-fin RF mixer architecture, three independent gates (MIDFET-T) operation and temperature characteristics," in VLSI Symp. Tech. Dig., 2005, pp. 200-201.
6. M. Masahara, Y. X. Liu, K. Sakamoto, K. Endo, T. Matsukawa, K. Ishii, T. Sekigawa, H. Yamauchi, H. Tanoue, S. Kanemaru, H. Koike, and E. Suzuki, "Demonstration, analysis, and device design considerations for independent DG MOSFETs," IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 2046-2053, Sep. 2005.
7. Y. X. Liu, K. Endo, M. Masahara, E. Sugimata, T. Matsukawa, K. Ishii, H. Yamauchi, T. Shimizu, K. Sakamoto, S. O'uchi, T. Sekigawa, and E. Suzuki, "Advanced FinFET technology: TiN metal-gate CMOS and 3T/4T device integration," in Proc. IEEE Int. SOI Conf., 2005, pp. 219-220.
8. M. Masahara, R. Surdeanu, L. Witters, G. Doornbos, V. H. Nguyen, G. Van de bosch, C. Vrancken, K. Devriendt, F. Neuilly, E. Kunnen, M. Jurczak, and S. Biesemans, "Demonstration of asymmetric gate oxide thickness 4-terminal FinFETs," in Proc. IEEE Int. SOI Conf., 2006, pp. 165-166.
9. M.-H. Chiang, K. Kim, C.-T. Chuang, and C. Tretz, "High-density reduced-stack logic circuit techniques using independent-gate controlled doublegate devices," IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2370-2377, Sep. 2006.