Efficiency of body biasing in 90 nm CMOS for low power digital circuits

ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference

Volumn , Issue , 2004, Pages 175-178

  Von Arnim, Klaus ^a,b   Borinski, Eduardo ^a,c   Seegebrecht, Peter ^b   Fiedler, Horst ^c   Brederlow, Ralf ^a   Thewes, Roland ^a   Berthold, Jörg ^a   Pacha, Christian ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b UNIVERSITY OF KIEL   (Germany)

^c TU DORTMUND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CIRCUITS; ELECTRIC INVERTERS; GATES (TRANSISTOR); LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; OSCILLATORS (ELECTRONIC); THRESHOLD VOLTAGE;

FORWARD DIASING (FB); LOW-LEAKAGE DEVICES (LLD); POWER CIRCUITS; THICK-OXIDE DEVICES;

CMOS INTEGRATED CIRCUITS;

EID: 17644380683     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. K. Ishibashi et al., A 9μW 50MHz 32b adder using a self-adjusted forward body bias in SoCs, ISSCC 2003.
2. C. Neau, K. Roy, Optimal body bias selection for leakage improvement and process compensation over different technology generations, ISLPED 2003.
3. S.-F. Huang et al., Scalability and biasing strategy for CMOS with active well bias, VLSI Symposium 2001.
4. S.-F. Huang et al., High performance 50 nm CMOS devices for microprocessor and embedded processor core applications, IEDM 2001
5. Y. Tsividis, Operation and modeling of the MOS transistor, 2nd edition, WCB/McGraw-Hill, 1999.
6. K. Kanda et al., Design impact of positive temperature dependence on drain current in sub-1V CMOS VLSI's, IEEE Journal of Solid-State Circuits, Vol. 36, No. 10, Oct. 2001.
7. I. M. Filanovsky et al., Mutual compensation of mobility and threshold voltage temp. effects with applications in CMOS circuits, IEEE Trans. on Circuits and Systems I, Vol. 48, No. 7, Jul. 2001.