Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 3, 2004, Pages 501-510

  Narendra, Siva ^a   De, Vivek ^a   Borkar, Shekhar ^a   Antoniadis, Dimitri A ^b   Chandrakasan, Anantha P ^b  

^a INTEL CORPORATION   (United States)

^b Massachusetts Institute of Technology Cambridge   (United States)

Author keywords

CMOS; Leakage estimation; Leakage reduction; Subthreshold leakage; Within die variation

Indexed keywords

BIT ERROR RATE; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; REDUCTION; STATISTICAL METHODS; THRESHOLD VOLTAGE;

CONTROL SWITCHING POWER DISSIPATION; SUBTHRESHOLD LEAKAGE;

CMOS INTEGRATED CIRCUITS;

EID: 1542605495     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.821776     Document Type: Article

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