Optimal body bias selection for leakage improvement and process compensation over different technology generations

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 116-121

  Neau, C ^a   Roy, K ^a  

^a Purdue University   (United States)

Author keywords

Algorithm design and analysis; CMOS process; CMOS technology; Integrated circuit yield; Leakage current; MOS devices; Permission; Threshold voltage; Tunneling; Very large scale integration

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRON TUNNELING; LEAKAGE CURRENTS; LOW POWER ELECTRONICS; MOS DEVICES; POWER ELECTRONICS; THRESHOLD VOLTAGE; VLSI CIRCUITS;

ALGORITHM DESIGN AND ANALYSIS; BAND-TO-BAND TUNNELING LEAKAGE; CMOS PROCESSS; CMOS TECHNOLOGY; PERMISSION; PROCESS COMPENSATION; SOURCE/DRAIN JUNCTIONS; SUB-THRESHOLD LEAKAGE;

BIAS VOLTAGE;

EID: 1542359166     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231846     Document Type: Conference Paper

References (14)

1. T. Kuroda, et. al., "A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D Discrete Cosine Transform Processor with Variable Threshold-Voltage (VT) Scheme," IEEE JSSC, vol. 31, No. 11, Nov. 1996, pp. 1770-1779.
2. S-F. Huang, et al., "Scalability and Biasing Strategy for CMOS with Active Well Bias," 2001 Symp. on VLSI Tech. Digest of Technical Papers, pp. 107-108.
3. th NASA Symposium on VLSI Design, 1999, pp. 2.3.1-2.3.9.
4. A. Keshavarzi, et al., "Forward Body Bias for Microprocessors in 130nm Technology Generation and Beyond," 2002 Symposium on VLSI Technology Digest of Technical Papers. pp. 312-315.
5. J. Tschanz, et. al., "Adaptive Body Bias for Reducing Impacs of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage," 2002 ISSCC Digest of Technical Papers, pp 477-479.
6. V. De, et. al., "Techniques for Leakage Power Reduction,"Design of High-Performance Microprocessor Circuits, Piscataway, NJ: IEEE Press, 2001, pp. 48-52.
7. Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, New York, USA: Cambridge University Press, 1998.
8. K. Schuegraf and C. Hu, "Hole Injection SiO2 Breakdown Model for Very Low Voltage Lifetime Extrapolation," IEEE Trans. on Electron Devices, vol.41, May 1994, pp. 761-767.
9. Berkeley Predictive Technology Model, U.C. Berkeley, http://www-devices.eecs.berkeley.edu/~ptm/
10. BSIM4. BSIM Group, U.C. Berkeley, http://www-devices.eecs.berkeley.edu/bsim3/bsim4.html
11. Taurus-Device Simulator. Synopsys, 2002.
12. Z. Chen, et. al. "Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks," Proc. of ISLPED, 1998, pp. 239-244.
13. "Well-Tempered" Bulk-Si NMOS Device Home Page, Microsystems Technology Laboratory, MIT, http://www-mtl.mit.edu/Well/
14. International Technology Roadmap for Semiconductors 2001 Edition, Semiconductor Industry Association, http://public.itrs.net