Comparison of modeling approaches for the capacitance-voltage and current-voltage characteristics of advanced gate stacks

IEEE Transactions on Electron Devices

Volumn 54, Issue 1, 2007, Pages 106-114

  Palestri, P ^a   Barin, N ^b   Brunel, D ^c   Busseret, C ^c   Campera, A ^d   Childs, P A ^e   Driussi, F ^a   Fiegna, C ^b   Fiori, G ^d   Gusmeroli, R ^f   Iannaccone, G ^d   Karner, M ^g   Kosina, H ^g   Lacaita, A L ^f   Langer, E ^g   Majkusiak, B ^h   Monzio Compagnoni, C ^f   Poncet, A ^c   Sangiorgi, E ^b   Selmi, L ^a   Spinelli, A S ^f   Walczak, J ^h   more..

^a UNIVERSITY OF UDINE   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c CNRS   (France)

^d UNIVERSITY OF PISA   (Italy)

^e UNIVERSITY OF BIRMINGHAM   (United Kingdom)

^f POLITECNICO DI MILANO   (Italy)

^g VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

^h WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

Gate leakage; Gate stacks; High k dielectric materials; Tunneling

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; DIELECTRIC DEVICES; LEAKAGE CURRENTS; MATHEMATICAL MODELS; SILICA;

GATE LEAKAGE; GATE STACKS;

ELECTRIC POTENTIAL;

EID: 33846118707     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.887226     Document Type: Article

References (42)

1. International Technology Roadmap for Semiconductor, 2005.
2. S.-H. Lo, D. Buchanan, Y. Taur, and W. Wang, "Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultrathin-oxide nMOSFETs," IEEE Electron Device Lett., vol. 18, no. 5, pp. 209-211, May 1997.
3. J. Suehle, "Ultrathin gate oxide reliability: Physical models, statistics, and characterization," IEEE Trans. Electron Devices, vol. 49, no. 6, pp. 958-971, Jun. 2002.
4. H. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S.-I. Nakamura, M. Saito, and H. Iwai, "1.5 nm direct-tunneling gate oxide Si MOSFETs," IEEE Trans. Electron Devices, vol. 43, no. 8, pp. 1233-1242, Aug. 1996.
5. W. Henson, N. Yang, S. Kubicek, E. Vogel, J. Wortman, K. D. Meyer, and A. Naem, "Analysis of leakage currents and impact on OFF-state power consumption for CMOS technology in the 100-nm regime," IEEE Trans. Electron Devices, vol. 47, no. 7, pp. 1393-1400, Jul. 2000.
6. C.-H. Choi, K.-Y. Nam, Z. Yu, and R. Dutton, "Impact of gate direct tunneling current on circuit performance: A simulation study," IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2823-2829, Dec. 2001.
7. 2," J. Appl. Phys., vol. 40, no. 1, pp. 278-283, Jan. 1969.
8. 2," Solid State Electron., vol. 20, no. 1, pp. 11-18, Jan. 1977.
9. F. Rana, S. Tiwari, and D. Buchanan, "Self-consistent modeling of accumulation layers and tunneling currents through very thin oxides," Appl. Phys. Lett., vol. 69, no. 8, pp. 1104-1106, Aug. 1996.
10. C. Bowen, C. Fernando, G. Klimeck, A. Chatterjee, D. Blanks, R. Lake, J. Hu, J. Davis, M. Kulkarni, S. Hattangady, and I.-C. Chen, "Physical oxide thickness extraction and verification using quantum-mechanical simulation," in IEDM Tech. Dig., 1997, pp. 869-872.
11. W.-K. Shih, E. Wang, S. Jallepalli, F. Leon, C. Maziar, and A. Tasch, "Modeling gate leakage current in nMOS structures due to tunneling through an ultra-thin oxide," Solid State Electron., vol. 42, no. 6, pp. 997-1006, Jun. 1998.
12. E. Cassan, "On the reduction of direct tunneling leakage through ultrathin gate oxides by a one-dimensional Schrödinger-Poisson solver," J. Appl. Phys., vol. 87, no. 11, pp. 7931-7939, Jun. 2000.
13. A. Ghetti, C.-T. Liu, M. Mastrapasqua, and E. Sangiorgi, "Characterization of tunneling current in ultra-thin gate oxide," Solid State Electron., vol. 44, no. 9, pp. 1523-1531, Sep. 2000.
14. S. Mudanai, Y.-Y. Fan, Q. Ouyang, A. Tasch, and S. K. Banerjee, "Modeling of direct tunneling current through gate dielectric stacks," IEEE Trans. Electron Devices, vol. 47, no. 10, pp. 1851-1857, Oct. 2000.
15. 2 gate oxides from microscopic models," J. Appl. Phys., vol. 89, no. 1, pp. 348-363, Jan. 2001.
16. R. Clerc, A. Spinelli, G. Ghibaudo, and G. Pananakakis, "Theory of direct tunneling current in metal-oxide-semiconductor structures," J. Appl. Phys., vol. 91, no. 3, pp. 1400-1409, Feb. 2002.
17. K. Ahmed, E. Ibok, G. Bains, D. Chi, B. Ogle, J. J. Wortman, and J. R. Hauser, "Comparative physical and electrical metrology of ultrathin oxides in the 6 to 1.5 nm regime," IEEE Trans. Electron Devices, vol. 47, no. 7, pp. 1349-1354, Jul. 2000.
18. C. A. Richter, A. R. Hefner, and E. M. Vogel, "A comparison of quantum-mechanical capacitance-voltage simulators," IEEE Electron Device Lett., vol. 22, no. 1, pp. 35-37, Jan. 2001.
19. A. Dalla Serra, A. Abramo, P. Palestri, L. Selmi, and F. Widdershoven, "Closed- and open-boundary models for gate-current calculation in n-MOSFETs," IEEE Trans. Electron Devices, vol. 48, no. 8, pp. 1811-1815, Aug. 2001.
20. V. Temple, M. Green, and J. Shewchun, "Equilibrium-to-nonequilibrium transistion in MOS (surface oxide) tunnel diode," J. Appl. Phys., vol. 45, no. 11, pp. 4934-4943, Nov. 1974.
21. J. Bardeen, "Tunneling from a many-particle point of view," Phys. Rev. Lett., vol. 6, no. 2, pp. 57-59, Jan. 1961.
22. W. Harrison, "Tunneling from an independent-particle point of view," Phys. Rev. B, Condens. Matter, vol. 123, no. 1, pp. 85-87, 1961.
23. P. J. Price, "Resonant tunneling via an accumulation layer," Phys. Rev. B, Condens. Matter, vol. 45, no. 16, pp. 9042-9045, Apr. 1992.
24. C. Fernando and W. Frensley, "An efficient method for the numerical evaluation of resonant states," J. Appl. Phys., vol. 76, no. 5, pp. 2881-2886, Sep. 1994.
25. G. Gildenblat, B. Gelmont, and S. Vatannia, "Resonant behavior, symmetry, and singularity of the transfer matrix in asymmetric tunneling structures," J. Appl. Phys., vol. 77, no. 12, pp. 6327-6331, Jun. 1995.
26. M. Karner, A. Gehring, and H. Kosina, "Efficient calculation of life time based direct tunneling through stacked dielectrics," in Proc. Workshop Model. and Simul. Electron Devices, Pisa, Italy, Jul. 4-5, 2005, pp. 97-98.
27. M. Karner, A. Gehring, H. Kosina, and S. Selberherr, "Efficient calculation of quasi-bound state tunneling in CMOS devices," in Proc. SISPAD, 2005, pp. 35-38.
28. N. Barin and C. Fiegna, "Analysis of double-gate MOS structures by solving Poisson and Schrödinger equations with open boundaries," in Proc. 5th Eur. Workshop ULtimate Integr. Silicon, Leuven, Belgium, Mar. 11-12, 2004, pp. 93-96.
29. W. Lui and M. Fukuma, "Exact solution of the Schrödinger equation across an arbitrary one-dimensional piecewise-linear potential barrier," J. Appl. Phys., vol. 60, no. 5, p. 1555, Sep. 1986.
30. G. Iannaccone and B. Pellegrini, "Compact formula for the density of states in a quantum well," Phys. Rev. B, Condens. Matter, vol. 53, no. 4, pp. 2020-2025, Jan. 1996.
31. D. Ielmini, A. Spinelli, M. A. Rigamonti, and A. L. Lacaita, "Modeling of SILC based on electron and hole tunneling - Part I: Transient effects," IEEE Trans. Electron Devices, vol. 47, no. 6, pp. 1258-1265, Jun. 2000.
32. A. Poncet, C. Faugeras, and M. Mouis, "Simulation of 2-D quantum effects in ultra-short channel MOSFETs by a finite element method," Eur. J. Phys., vol. 15, no. 2, pp. 117-121, Aug. 2001.
33. S. Gennai and G. Iannaccone, "Detailed calculation of the vertical electric field in thin oxide MOSFETs," Electron. Lett., vol. 35, no. 21, pp. 1881-1883, Oct. 1999.
34. G. Iannaccone and S. Gennai, "Program, erase and retention times of thinoxide Flash-EEPROMs," VLSI Des., vol. 13, no. 1-4, pp. 431-434, 2001.
35. G. Iannaccone, F. Crupi, B. Neri, and S. Lombardo, "Theory and experiment of suppressed shot noise in stress-induced leakage currents," IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 1363-1369, May 2003.
36. A. Campera, G. Iannaccone, F. Crupi, and G. Groeseneken, "Extraction of physical parameters of alternative high-k stacks through comparison between measurements and quantum simulations," in Proc. 6th Eur. Workshop ULtimate Integr. Silicon, Bologna, Italy, Apr. 7-8, 2005, pp. 35-38.
37. A. Spinelli, A. Benvenuti, and A. Pacelli, "Self-consistent 2-D model for quantum effects in n-MOS transistors," IEEE Trans. Electron Devices, vol. 45, no. 6, pp. 1342-1349, Jun. 1998.
38. A. Pacelli, A. Spinelli, and L. Perron, "Carrier quantization at flat bands in MOS devices," IEEE Trans. Electron Devices, vol. 46, no. 2, pp. 383-387, Feb. 1999.
39. B. Majkusiak, "Theoretical modeling of the double gate MOS resonant tunneling diode," in Proc. 4th Eur. Workshop Ultimate Integr. Silicon, Udine, Italy, Mar. 20-21, 2003, pp. 147-150.
40. T. Kauerauf, B. Govoreanu, R. Degraeve, and G. Groeseneken, "Scaling CMOS: Finding the optimal gate dielectric," in Proc. 5th Eur. Workshop ULtimate Integr. Silicon, Leuven, Belgium, Mar. 11-12, 2004, pp. 35-38.
41. J. Schmitz, F. Cubaynes, R. Havens, R. Kort, A. Scholten, and L. Tiemeijer, "RF capacitance-voltage characterization of MOSFETs with high leakage dielectrics," IEEE Electron Device Lett., vol. 24, no. 1, pp. 37-39, Jan. 2003.
42. N. Yang, W. K. Henson, J. R. Hauser, and J. J. Wortman, "Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices," IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1464-1471, Jul. 1999.