Double-gate SOI devices for low-power and high-performance applications

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 217-224

  Roy, Kaushik ^a   Mahmoodi, Hamid ^b   Mukhopadhyay, Saibal ^a   Ananthan, Hari ^a   Bansal, Aditya ^a   Cakici, Tamer ^a  

^a Purdue University   (United States)

^b SAN FRANCISCO STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DOUBLE GATE (DG) TRANSISTORS; PARALLEL TRANSISTORS; SCHMITT TRIGGERS; SENSE AMPLIFIERS; WIDTH QUANTIZATION;

CAPACITANCE; CMOS INTEGRATED CIRCUITS; CRITICAL PATH ANALYSIS; LOGIC CIRCUITS; SILICON ON INSULATOR TECHNOLOGY; STATIC RANDOM ACCESS STORAGE; SWITCHING CIRCUITS;

NETWORKS (CIRCUITS);

EID: 33751414310     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560067     Document Type: Conference Paper

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