A new cell-based performance metric for novel CMOS device architectures

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 743-746

  Christie, P ^a   Heringa, A ^a   Doornbos, G ^a   Kumar, A ^a   Nguyen, V H ^a   Ng, R K M ^a   Garg, M ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; GATES (TRANSISTOR); LEAKAGE CURRENTS; NAND CIRCUITS; PERFORMANCE; CELLS; CMOS INTEGRATED CIRCUITS; CYTOLOGY;

CAPACITIVE LOADS; INTERCONNECT LAYERS; MULTI-GATE DEVICES; POWER ANALYSIS;

CMOS INTEGRATED CIRCUITS; MULTIPLE-GATE FIELD-EFFECT TRANSISTORS;

CELL-BASED; CMOS DEVICES; CMOS TECHNOLOGY; DEVICE ARCHITECTURES; MULTIGATE DEVICES; ON DYNAMICS; PERFORMANCE METRICES; POWER; SYSTEM-LEVEL PERFORMANCE; TECHNOLOGY CHOICES;

EID: 21644440309     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

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3. P. Christie, "A differential equation for placement analysis," IEEE Trans. on VLSI, 9(6), pp. 913-921, December 2001.
4. M. Iqbal, A. Sharkawy, U. Hameed, and P. Christie, "Stochastic wire length sampling for cycle time estimation," Proc. IEEE/ACM System Level Interconnect Prediction Workshop, pp. 91-96, March 2002, ACM Press.