A highly threshold voltage-controllable 4T FinFET with an 8.5-nm-thick Si-Fin channel

IEEE Electron Device Letters

Volumn 25, Issue 7, 2004, Pages 510-512

  Liu, Yongxun ^a   Masahara, Meishoku ^a   Ishii, Kenichi ^a   Sekigawa, Toshihiro ^a   Takashima, Hidenori ^a   Yamauchi, Hiromi ^a   Suzuki, Eiichi ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; ELECTRON BEAM LITHOGRAPHY; ETCHING; GATES (TRANSISTOR); SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; THERMAL DIFFUSION; THRESHOLD VOLTAGE; TRANSMISSION ELECTRON MICROSCOPY; VLSI CIRCUITS; VOLTAGE CONTROL;

DOUBLE GATE MOSFET; FINFET; FOUR TERMINAL FINFET; ORIENTATION DEPENDENT ETCHING; SCANNING TRANSMISSION ELECTRON MICROSCOPY; SHORT CHANNEL EFFECTS; THRESHOLD VOLTAGE CONTROL; WET ETCHING;

MOSFET DEVICES;

EID: 3342955721     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.831205     Document Type: Article

References (14)

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