메뉴 건너뛰기




Volumn 54, Issue 12, 2007, Pages 3361-3368

Analysis of options in double-gate MOS technology: A circuit perspective

Author keywords

Asymmetric double gate MOS (DGMOS); DGMOSFETs; Independent gate technology; MOSFET; Schmitt trigger; Symmetric DGMOS; Trigger circuits

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ENERGY DISSIPATION; GATES (TRANSISTOR); TRIGGER CIRCUITS;

EID: 36849035755     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.909057     Document Type: Article
Times cited : (34)

References (21)
  • 1
    • 0036507826 scopus 로고    scopus 로고
    • Maintaining the benefits of CMOS scaling when scaling bogs down
    • E. J. Nowak, "Maintaining the benefits of CMOS scaling when scaling bogs down," IBM J. Res. Develop., vol. 46, no. 2/3, pp. 169-180, 2002.
    • (2002) IBM J. Res. Develop , vol.46 , Issue.2-3 , pp. 169-180
    • Nowak, E.J.1
  • 2
    • 0035714565 scopus 로고    scopus 로고
    • M. Ieong, E. C. Jones, T. Kanarsky, Z. Ren, O. Dokumaci, R. A. Roy, L. Shi, T. Furukawa, Y. Taur, R. J. Miller, and H. S. P. Wong, Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs, in IEDM Tech. Dig., Dec. 2001, pp. 19.6.1-19.6.4.
    • M. Ieong, E. C. Jones, T. Kanarsky, Z. Ren, O. Dokumaci, R. A. Roy, L. Shi, T. Furukawa, Y. Taur, R. J. Miller, and H. S. P. Wong, "Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs," in IEDM Tech. Dig., Dec. 2001, pp. 19.6.1-19.6.4.
  • 3
    • 0036564015 scopus 로고    scopus 로고
    • Speed superiority of scaled double-gate CMOS
    • May
    • J. G. Fossum, G. Lixin, and C. Meng Hsueh, "Speed superiority of scaled double-gate CMOS," IEEE Trans. Electron Devices, vol. 49, no. 5, pp. 808-811, May 2002.
    • (2002) IEEE Trans. Electron Devices , vol.49 , Issue.5 , pp. 808-811
    • Fossum, J.G.1    Lixin, G.2    Meng Hsueh, C.3
  • 4
    • 34247165336 scopus 로고    scopus 로고
    • Impact of FD-SOI on deep-sub-100-nm CMOS LSIs - A view of memory designers
    • Oct
    • K. Itoh, M. Yamaoka, and T. Kawahara, "Impact of FD-SOI on deep-sub-100-nm CMOS LSIs - A view of memory designers," in Proc. IEEE Int. SOI Conf., Oct. 2006, pp. 103-104.
    • (2006) Proc. IEEE Int. SOI Conf , pp. 103-104
    • Itoh, K.1    Yamaoka, M.2    Kawahara, T.3
  • 6
    • 36849032126 scopus 로고    scopus 로고
    • J. Kedzierski, D. M. Fried, E. J. Nowak, T. Kanarsky, J. H. Rankin, H. Hanafi, W. Natzle, D. Boyd, Y. Zhang, R. A. Roy, J. Newbury, C. Yu, Q. Yang, P. Saunders, C. P. Willets, A. Johnson, S. P. Cole, H. E. Young, N. Carpenter, D. Rakowski, B. A. Rainey, P. E. Cottrell, M. Ieong, and H. S. P. Wong, High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices, in IEDM Tech. Dig., Dec. 2001, pp. 19.5.1-19.5.4.
    • J. Kedzierski, D. M. Fried, E. J. Nowak, T. Kanarsky, J. H. Rankin, H. Hanafi, W. Natzle, D. Boyd, Y. Zhang, R. A. Roy, J. Newbury, C. Yu, Q. Yang, P. Saunders, C. P. Willets, A. Johnson, S. P. Cole, H. E. Young, N. Carpenter, D. Rakowski, B. A. Rainey, P. E. Cottrell, M. Ieong, and H. S. P. Wong, "High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices," in IEDM Tech. Dig., Dec. 2001, pp. 19.5.1-19.5.4.
  • 9
    • 0142154823 scopus 로고    scopus 로고
    • A low power four transistor Schmitt Trigger for asymmetric double gate fully depleted SOI devices
    • Oct
    • T. Cakici, A. Bansal, and K. Roy, "A low power four transistor Schmitt Trigger for asymmetric double gate fully depleted SOI devices," in Proc. IEEE Int. SOI Conf., Oct. 2003, pp. 21-22.
    • (2003) Proc. IEEE Int. SOI Conf , pp. 21-22
    • Cakici, T.1    Bansal, A.2    Roy, K.3
  • 10
    • 0036905779 scopus 로고    scopus 로고
    • Effect of back-gate biasing on the performance and leakage control in deeply scaled SOI MOSFETs
    • Oct
    • A. Khakifirooz and D. A. Antoniadis, "Effect of back-gate biasing on the performance and leakage control in deeply scaled SOI MOSFETs," in Proc. IEEE Int. SOI Conf., Oct. 2002, pp. 58-59.
    • (2002) Proc. IEEE Int. SOI Conf , pp. 58-59
    • Khakifirooz, A.1    Antoniadis, D.A.2
  • 11
    • 16244376777 scopus 로고    scopus 로고
    • High performance and low power domino logic using independent gate control in double-gate SOI MOSFETs
    • Oct
    • H. Mahmoodi, S. Mukhopadhyay, and K. Roy, "High performance and low power domino logic using independent gate control in double-gate SOI MOSFETs," in Proc. IEEE Int. SOI Conf., Oct. 2004, pp. 67-68.
    • (2004) Proc. IEEE Int. SOI Conf , pp. 67-68
    • Mahmoodi, H.1    Mukhopadhyay, S.2    Roy, K.3
  • 13
    • 0035250378 scopus 로고    scopus 로고
    • Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices
    • Feb
    • K. Kim and J. G. Fossum, "Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices," IEEE Trans. Electron Devices, vol. 48, no. 2, pp. 294-299, Feb. 2001.
    • (2001) IEEE Trans. Electron Devices , vol.48 , Issue.2 , pp. 294-299
    • Kim, K.1    Fossum, J.G.2
  • 14
    • 16244379510 scopus 로고    scopus 로고
    • Novel process for fully self-aligned planar ultrathin body double-gate FET
    • Oct
    • R. S. Shenoy and K. C. Saraswat, "Novel process for fully self-aligned planar ultrathin body double-gate FET," in Proc. IEEE Int. SOI Conf. Oct. 2004, pp. 190-191.
    • (2004) Proc. IEEE Int. SOI Conf , pp. 190-191
    • Shenoy, R.S.1    Saraswat, K.C.2
  • 15
    • 33748558677 scopus 로고    scopus 로고
    • Design of high performance sense amplifier using independent gate control in sub-50 nm double-gate MOSFET
    • S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Design of high performance sense amplifier using independent gate control in sub-50 nm double-gate MOSFET," in Proc. IEEE Int. Symp. Quality Electron. Des., 2005, pp. 490-495.
    • (2005) Proc. IEEE Int. Symp. Quality Electron. Des , pp. 490-495
    • Mukhopadhyay, S.1    Mahmoodi, H.2    Roy, K.3
  • 16
    • 33847122571 scopus 로고    scopus 로고
    • Modeling and optimization approach to robust and low-power FinFET SRAM design in nanoscale era
    • A. Bansal, S. Mukhopadhyay, and K. Roy, "Modeling and optimization approach to robust and low-power FinFET SRAM design in nanoscale era," in Proc. IEEE Custom Integr. Circuits Conf., 2005, pp. 830-833.
    • (2005) Proc. IEEE Custom Integr. Circuits Conf , pp. 830-833
    • Bansal, A.1    Mukhopadhyay, S.2    Roy, K.3
  • 17
    • 33845895851 scopus 로고    scopus 로고
    • Synopsys, Mountain View, CA, Sep
    • Taurus Device User Guide, Synopsys, Mountain View, CA, Sep. 2004.
    • (2004) Taurus Device User Guide
  • 18
    • 0026106011 scopus 로고
    • Delay analysis of series-connected MOSFET circuits
    • Feb
    • T. Sakurai and A. R. Newton, "Delay analysis of series-connected MOSFET circuits," IEEE J. Solid-State Circuits, vol. 26, no. 2, pp. 122-131, Feb. 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , Issue.2 , pp. 122-131
    • Sakurai, T.1    Newton, A.R.2
  • 20
    • 0036458455 scopus 로고    scopus 로고
    • A comparative study of threshold variations in symmetric and asymmetric undoped double-gate MOSFETs
    • Oct
    • Q. Chen and J. D. Meindl, "A comparative study of threshold variations in symmetric and asymmetric undoped double-gate MOSFETs," in Proc. IEEE Int. SOI Conf., Oct. 2002, pp. 30-31.
    • (2002) Proc. IEEE Int. SOI Conf , pp. 30-31
    • Chen, Q.1    Meindl, J.D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.