A CMOS time-to-digital converter (TDC) based on a cyclic time domain successive approximation interpolation method

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 11, 2009, Pages 3067-3078

  Mantyniemi, Antti ^a   Rahkonen, Timo ^a   Kostamovaara, Juha ^a  

^a UNIVERSITY OF OULU   (Finland)

Author keywords

All digital delay locked loop (ADDLL); CMOS integrated circuits; Delay line interpolation; Delay locked loop (DLL); Digital to time converter (DTC); Successive approximation register (SAR); Time digitizer; Time to digital converter (TDC)

Indexed keywords

ALL-DIGITAL DELAY-LOCKED LOOP (ADDLL); DELAY LINE INTERPOLATION; DELAY-LOCKED LOOP (DLL); DIGITAL-TO-TIME CONVERTER (DTC); SUCCESSIVE APPROXIMATION REGISTER (SAR); TIME DIGITIZER; TIME-TO-DIGITAL CONVERTER (TDC);

ANALOG TO DIGITAL CONVERSION; APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DIGITAL INTEGRATED CIRCUITS; FREQUENCY CONVERTERS; INTEGRATED CIRCUITS; INTERPOLATION; LUMPED PARAMETER NETWORKS; MOS CAPACITORS; SYNTHETIC APERTURES; TABLE LOOKUP; WAVES;

TIME DOMAIN ANALYSIS;

EID: 70449484373     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2032260     Document Type: Article

References (52)

1. A. V. Akindinov et al., "Design aspects and prototype test of a very precise TDC system implemented for the multigap RPC of the ALICETOF," Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol.533, no.1-2, pp. 178-182, Nov. 2004.
2. E. Räisänen-Ruotsalainen, T. Rahkonen, and J. Kostamovaara, "An integrated time-to-digital converter with 30-ps single-shot precision," IEEE J. Solid-State Circuits, vol.35, no.10, pp. 1507-1510, Oct. 2000. (Pubitemid 30968530)
3. M. A. Abas, G. Russell, and D. J. Kinniment, "Built-in time measurement circuits-a comparative design study," IET Comput. Digit. Tech, vol.1, no.2, pp. 87-97, Mar. 2007.
4. J. Rivoir, "Fully-digital time-to-digital converter for ATE with autonomous calibration," in Proc. IEEE Int. Test Conf., Oct. 2006, pp. 1-10.
5. R. B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J. L. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung, J. Koh, S. John, I. Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O. E. Eliezer, E. de Obaldia, and P. T. Balsara, "All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS," IEEE J. Solid-State Circuits, vol.39, no.12, pp. 2278-2291, Dec. 2004.
6. R. Tonietto, E. Zuffetti, R. Castello, and I. Bietti, "A 3MHz bandwidth low noise RF all digital PLL with 12 ps resolution time to digital converter," in Proc. European Solid-State Circuits Conf., ESSCIRC, Sep. 2006, pp. 150-153.
7. A. H. Chan and G. W. Roberts, "A jitter characterization system using a component-invariant vernier delay line," IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol.12, no.1, pp. 79-95, Jan. 2004.
8. V. Gutnik and A. Chandrakasan, "On-chip picosecond time measurement," in Proc. IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2000, pp. 52-53.
9. D. J. Kinniment, O. V. Maevsky, A. Bystrov, G. Russell, and A. V. Yakolev, "On-chip structures for timing measurement and test," in Proc. 8th Int. Symp. Asynchronous Circuits and Systems, Apr. 2002, pp. 190-197.
10. P. M. Levine and G. W. Roberts, "High-resolution flash time-to-digital conversion and calibration for system-on-chip testing," in Proc. IEE. Computers and Digital Techniques, May 2005, vol.152, pp. 415-426.
11. K. Nose, M. Kajita, and M. Mizuno, "A 1-ps resolution jitter-measurement macro using interpolated jitter oversampling," IEEE J. Solid-State Circuits, vol.41, no.12, pp. 2911-2920, Dec. 2006. (Pubitemid 44955516)
12. T. Xia, H. Zheng, J. Li, and A. Ginawi, "Self-refereed on-chip jitter measurement circuit using vernier oscillators," in Proc. IEEE Computer Society Annual Symp. VLSI, May 2005, pp. 218-223.
13. R. Nutt, "Digital time intervalometer," Rev. Sci. Instrum., vol.39, no.9, pp. 1342-1345, Sep. 1968.
14. R. B. Staszewski, J. L. Wallberg, S. Rezeq, C.-M. Hung, O. E. Eliezer, S. K. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, "All-digital PLL and transmitter for mobile phones," IEEE J. Solid- State Circuits, vol.40, no.12, pp. 2469-2482, Dec. 2005.
15. A. Mäntyniemi, T. Rahkonen, and J. Kostamovaara, "An integrated 9-channel time digitizer with 30 ps resolution," in IEEE Int. Solid- State Circuits Conf. Dig. Tech. Papers, ISSCC, Feb. 2002, vol.1, pp. 266-267, 465.
16. J.-P. Jansson, A. Mäntyniemi, and J. Kostamovaara, "A CMOS time-to-digital converter with better than 10 ps single-shot precision," IEEE J. Solid-State Circuits, vol.41, no.6, pp. 1286-1296, Jun. 2006.
17. Y. Arai, "A high-resolution time digitizer utilizing dual PLL circuits," in Proc. IEEE Nuclear Science Symp. Conf. Rec., Oct. 2004, vol.2, pp. 969-973.
18. J. F. Genat, "High resolution time-to-digital converters," Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol.315, no.1-3, pp. 411-414, May 1992.
19. P. Dudek, S. Szczepański, and J. V. Hatfield, "High resolution CMOS time-to-digital converters utilizing a Vernier delay line," IEEE Trans. Solid-State Circuits, vol.35, no.2, pp. 240-247, Feb. 2000.
20. A. S. Yousif and J. W. Haslett, "A fine resolution TDC architecture for next generation PET imaging," IEEE Trans. Nucl. Sci., vol.54, no.10, pp. 1574-1582, Oct. 2007.
21. M. Mota and J. Christiansen, "A high-resolution time interpolator based on a delay locked loop and an RC delay line," IEEE J. Solid-State Circuits, vol.34, no.10, pp. 1360-1366, Oct. 1999.
22. M. Mota, J. Christiansen, S. Debieux, V. Ryjov, P. Moreira, and A. Marchioro, "A flexible multi-channel high-resolution time-to-digital converter ASIC," in Nuclear Science Symp. Conf. Rec., Oct. 2000, vol.2, pp. 9/155-9/159.
23. P. Chen, C.-C. Chen, J.-C. Zheng, and Y.-S. Shen, "A PVT insensitive vernier-based time-to-digital converter with extended input range and high accuracy," IEEE Trans. Nucl. Sci., vol.54, no.4, pp. 294-302, Apr. 2007.
24. M. A. Abas, G. Russell, and D. J. Kinniment, "Embedded high-resolution delay measurement system using time amplification," IET Comput. Digit. Tech., vol.1, no.2, pp. 77-86, Mar. 2007.
25. M. Oulmane and G. W. Roberts, "A CMOS time amplifier for femtosecond resolution timing measurement," in Proc. Int. Symp. Circuits and Systems, ISCAS, May 2004, vol.1, pp. 509-512.
26. M. Lee and A. Abidi, "A 9 b, 1.25 ps resolution coarse-fine time-to- Digital converter in 90 nm CMOS that amplifies a time residue," IEEE J. Solid-State Circuits, vol.43, no.4, pp. 769-777, Apr. 2008.
27. K. Minami, M. Mizuno, H. Yamaguchi, T. Nakano, Y. Matsushima, Y. Sumi, T. Sato, H. Yamashida, and H. Y. Yamashina, "A 1 GHz portable digital delay-locked loop with infinite phase capture ranges," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, ISSCC, Feb. 2000, pp. 350-351, 469.
28. T. E. Rahkonen and J. T. Kostamovaara, "The use of stabilized CMOS delay lines for the digitization of short time intervals," IEEE J. Solid- State Circuits, vol.28, no.8, pp. 887-894, Aug. 1993.
29. C.-C. Chen, P. Chen, C.-S. Hwang, and W. Chang, "A precise cyclic CMOS time-to-digital converter with low thermal sensitivity," IEEE Trans. Nucl. Sci., vol.52, no.4, pp. 834-838, Aug. 2005.
30. K. Karadamoglou, N. P. Paschalidis, E. Sarris, N. Stamatopoulos, G. Kottaras, and V. Paschalidis, "An 11-bit high-resolution and adjustable-range CMOS time-to-digital converter for space science instruments," IEEE J. Solid-State Circuits, vol.39, no.1, pp. 214-222, Jan. 2004.
31. S. Tisa, A. Lotito, A. Giudice, and F. Zappa, "Monolithic time-to-digital converter with 20 ps resolution," in Proc. European Solid-State Circuits Conf., ESSCIRC, Sep. 2003, pp. 465-468.
32. S. Henzler, S. Koeppe, W. Kamp, R. Kuenemund, and D. Schmitt-Landsiedel, "A local passive time interpolation concept for variation-tolerant high-resolution time-to-digital conversion," IEEE J. Solid-State Circuits, vol.43, no.7, pp. 1666-1676, Jul. 2008.
33. A. Mäntyniemi, T. Rahkonen, and J. Kostamovaara, "A high resolution digital CMOS time-to-digital converter based on nested delay locked loops," in Proc. IEEE Int. Symp. Circuits and Systems, ISCAS, Jun. 1999, vol.2, pp. 537-540.
34. C.-S. Hwang, P. Chen, and H.-W. Tsao, "A high-precision time-todigital converter using a two-level conversion scheme," IEEE Trans. Nucl. Sci., vol.51, no.8, pp. 1349-1352, Aug. 2004.
35. R. Szymanowski and J. Kalisz, "Field programmable gate array time counter with two-stage interpolation," Rev. Sci. Instrum., vol.76, no.4, 045104, Apr. 2005.
36. V. Ramakrishnan and P. T. Balsara, "A wide-range, high-resolution, compact,CMOStime to digital converter," in Proc. 19th Int. Conf. VLSI Design, Jan. 2006, p. 6.
37. H.-Y. Huang, S.-D. Wu, and Y.-J. Tsai, "A new cycle-time-to-digital converter with two level conversion scheme," in Proc. IEEE Int. Symp. Circuits and Systems, ISCAS, May 2007, pp. 2160-2163.
38. G.-K. Dehng, J.-M. Hsu, C.-Y. Yang, and S.-I. Liu, "Clock-deskew buffer using a SAR-controlled delay-locked loop," IEEE J. Solid-State Circuits, vol.35, no.8, pp. 1128-1136, Aug. 2000.
39. H.-H. Chang and S.-I. Liu, "A wide-range and fast-locking all-digital cycle-controlled delay-locked loop," IEEE J. Solid-State Circuits, vol.40, no.3, pp. 661-670, Mar. 2005.
40. M. Bazes, R. Ashuri, and E. Knoll, "An interpolating clock synthesizer," IEEE J. Solid-State Circuits, vol.31, no.9, pp. 1295-1301, Sep. 1996.
41. A. Mäntyniemi, T. Rahkonen, and J. Kostamovaara, "A 9-channel integrated time-to-digital converter with sub-nanosecond resolution," in Proc. 40th Midwest Symp. Circuits and Systems, MWSCAS, Aug. 1997, vol.1, pp. 189-192.
42. C. Hervé and K. Torki, "A 75 ps rms time resolution BiCMOS time to digital converter optimized for high rate imaging detectors," Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol.481, no.1-3, pp. 566-574, Apr. 2002.
43. I. Nissinen, A. Mäntyniemi, and J. Kostamovaara, "A CMOS time-to-digital converter based on a ring oscillator for a laser radar," in Proc. European Solid-State Circuits Conf., ESSCIRC, Sep. 2003, pp. 469-472.
44. J. Kostamovaara and R. Myllylä, "Time-to-digital converter with an analog interpolation circuit," Rev. Sci. Instrum., vol.57, no.11, pp. 2880-2885, Nov. 1986.
45. J. U. Horstmann, H. W. Eichel, and R. L. Coates, "Metastability behavior ofCMOSASIC flip-flops in theory and test," IEEE J. Solid-State Circuits, vol.24, pp. 146-157, Feb. 1989.
46. J. Kalisz, M. Pawlowski, and R. Pelka, "Error analysis and design of the Nutt time-interval digitiser with picosecond resolution," J. Phys. E: Sci. Instrum., vol.20, pp. 1330-1341, 1987.
47. J. Kalisz, R. Pelka, and A. Poniecki, "Precision time counter for laser ranging to satellites," Rev. Sci. Instrum., vol.65, no.3, pp. 736-741, Mar. 1994.
48. R. Pelka, J. Kalisz, and R. Szplet, "Nonlinearity correction of the integrated time-to-digital converter with direct coding," IEEE Trans. Instrum. Meas., vol.46, pp. 449-453, Apr. 1997.
49. A. Mäntyniemi, T. Rahkonen, and J. Kostamovaara, "A nonlinearitycorrected CMOS time digitizer IC with 20 ps single-shot precision," in Proc. Int. Symp. Circuits and Systems, ISCAS, May 2002, vol.1, pp. 513-516.
50. J. Doernberg, H. S. Lee, and D. A. Hodges, "Full-speed testing of A/D converters," IEEE J. Solid-State Circuits, vol.19, pp. 820-827, Dec. 1984.
51. F. Baronti, D. Lunardini, R. Roncella, and R. Saletti, "A self-calibrating delay-locked delay line with shunt-capacitor scheme," IEEE J. Solid- State Circuits, vol.39, pp. 384-387, Feb. 2004.
52. Hewlett-Packard Inc., Time interval averaging. Application note 162-171 [Online]. Available: http://www.hpmemory.org/an/pdf/an-162-1.pdf