A 1GHz portable digital delay-locked loop with infinite phase capture ranges

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 350-351

  Minami, K ^a   Mizuno, M ^a   Yamaguchi, H ^a   Nakano, T ^a   Matsushima, Y ^a   Sumi, Y ^a   Sato, T ^a   Yamashida, H ^a   Yamashina, M ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; JITTER; MOS DEVICES; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; WAVEFORM ANALYSIS;

DELAY LOCKED LOOPS (DLL); VARIABLE DELAY LINES (VDL);

ELECTRIC DELAY LINES;

EID: 0034428333     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A variable delay line PLL for CPU- coprocessor synchronization
2. Device-deyiation tolerant over-1GHz clock distribution scheme with skew-immune race-free impulse latch circuits
3. A semidigital dual delay-locked loop
4. A portable digital DLL for high-speed CMOS interface circuits