A 3MHz bandwidth low noise RF AU digital PLL with 12ps resolution time to digital converter

ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

Volumn , Issue , 2006, Pages 150-153

  Tonietto, R ^a   Zuffetti, E ^a   Castello, R ^a   Bietti, I ^b  

^a UNIVERSITY OF PAVIA   (Italy)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BUILDING BLOCKS; DIGITAL CONTROL LOOP; DIGITAL CONVERTER; HIGH RESOLUTION TIME;

ANALOG CIRCUITS; BANDWIDTH; CMOS INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; PHASE NOISE;

PHASE LOCKED LOOPS;

EID: 84865431137     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2006.307553     Document Type: Conference Paper

References (5)