A Jitter Characterization System Using a Component-Invariant Vernier Delay Line

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 1, 2004, Pages 79-95

  Chan, Antonio H ^a,b   Roberts, Gordon W ^a  

^a MCGILL UNIVERSITY   (Canada)

^b INSTITUTE FOR RESEARCH IN IMMUNOLOGY AND CANCER   (Canada)

Author keywords

Characterization; Component invariant; Frequency; Jitter; Measurement; Register transfer level (RTL); Synthesizable; Time; Vernier delay line (VDL)

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; FREQUENCIES; FREQUENCY DOMAIN ANALYSIS; OSCILLATORS (ELECTRONIC); SILICON; SPURIOUS SIGNAL NOISE; STATISTICAL METHODS;

COMPONENT-INVARIANT; REGISTER TRANSFER LEVEL (RTL); SYNTHESIZABLE; TIME; VERNIER DELAY LINE (VDL);

TIMING JITTER;

EID: 1342308084     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.820531     Document Type: Article

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