A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 4, 2008, Pages 769-777

  Lee, Minjae ^a,b   Abidi, Asad A ^a,b  

^a IEEE

^b University of California   (United States)

Author keywords

Coarse fine architecture; Open loop residue amplification; Subrange normalization; Time amplifier; Time to digital converter (TDC)

Indexed keywords

AMPLIFICATION; AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; CODES (SYMBOLS); DIGITAL INTEGRATED CIRCUITS; GAIN CONTROL;

COARSE FINE ARCHITECTURE; SUBRANGE NORMALIZATION; TIME AMPLIFIERS; TIME TO DIGITAL CONVERTERS (TDC);

ELECTRIC CONVERTERS;

EID: 41549133070     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.917405     Document Type: Conference Paper

References (14)

1. Y. Arai andT. Baba, "A CMOS time to digital converter VLSI for high-energy physics," in VLSI Circuits Symp. Dig., Aug. 1988, pp. 121-122.
2. R. B. Staszewski, D. Leipold, C-M. Hung, and P. T. Bolsara, "TDC-based frequency synthesizer for wireless applications," in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symp., Jun. 2004, pp. 215-218.
3. R. B. Staszewski et al., "1.3V 20ps time-to-digital converters for frequency synthesis in 90-nm CMOS," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 3, pp. 220-224, Mar. 2006.
4. P. Dudek, S. Szczepanski, and J. V. Hatfield, "A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line," IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 240-247, Feb. 2000.
5. K. Nose et al., "A lps-resolution jitter-measurement macro using interpolated jitter oversampling," in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 520-521.
6. M. Lee and A. A. Abidi, "A 9b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies time residue," in VLSI Circuits Symp. Dig., Jun. 2007, pp. 168-169.
7. A. M. Abas et al., "Time difference amplifier," Electmn. Lett., vol. 38, no. 23, pp. 1437-1438, Nov. 2002.
8. A. M. Abas, G. Russell, and D. J. Kinniment, "Design of sub 10-picoseconds on-chip time measurement circuit," in Proc. Design Automation Test Europe Conf., 2004, vol. 2, pp. 804-809.
9. J. P. Janson et al., "A CMOS time-to-digital converter with better than 10 ps single-shot precision," IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 286-1296, Jun. 2006.
10. C. S. Hwang, P. Chen, and H. W. Tsao, "A high-precision time-to-digital converter using a two-level conversion scheme," IEEE Trans. Nucl. Sci., vol. 5.1, no. 4, pp. 1349-1352, Aug. 2004.
11. S. Tisa et al., "Monolithic time-to-digital converter with 20 ps resolution," in Proc. ESSCIRC, Sep. 2003, pp. 465-468.
12. K. Karadamoglou et al., "An 11 -bit high-resolution and adjustable-range CMOS time-to-digital converter for space science instruments," IEEEJ. Solid-State. Circuits, vol. 39, no. 1, pp. 214-222, Jan. 2004.
13. B. Murmann andB. E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplication," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dec. 2003.
14. "Time interval averaging," Hewlett Packard Inc., Application note 162-1.