A PVT insensitive vernier-based time-to-digital converter with extended input range and high accuracy

IEEE Transactions on Nuclear Science

Volumn 54, Issue 2, 2007, Pages 294-302

  Chen, Poki ^a,b   Chen, Chun Chi ^a,b   Zheng, Jia Chi ^b,c   Shen, You G ^b  

^a IEEE   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

^c Sitronix Technology Corp   (Taiwan)

Author keywords

Phase locked loop; PVT sensitivity; Time to digital converter; Vernier delay line

Indexed keywords

PHASE-LOCKED LOOP; PVT SENSITIVITY; TIME-TO-DIGITAL CONVERTER; VERNIER DELAY LINE;

CALIBRATION; CMOS INTEGRATED CIRCUITS; INTERPOLATION; MEASUREMENT THEORY; OPTICAL RESOLVING POWER; PROBLEM SOLVING;

ANALOG TO DIGITAL CONVERSION;

EID: 34247254927     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2007.892944     Document Type: Article

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