A 1-ps resolution jitter-measurement macro using interpolated jitter oversampling

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 12, 2006, Pages 2911-2920

  Nose, Koichi ^a,b   Kajita, Mikihiro ^b   Mizuno, Masayuki ^a,b  

^a IEEE   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

Calibration; Integrated circuit measurement; Jitter measurement; Oversampling

Indexed keywords

FEED FORWARD CALIBRATION; INTEGRATED CIRCUIT MEASUREMENT; JITTER MEASUREMENT; JITTER OVERSAMPLING; OVERSAMPLING; RANGE CONTROL TECHNIQUE;

CALIBRATION; DATA TRANSFER; ELECTRIC DELAY LINES; INTERPOLATION; REAL TIME SYSTEMS;

JITTER;

EID: 33845645404     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.884402     Document Type: Conference Paper

References (9)

1. N. Abaskharoun and G. W. Roberts, "Circuits for on-chip sub-nanosecond signal capture and characterization," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2001, pp. 251-254.
2. D. Weinlader, R. Ho, C.-K. K. Yang, and M. Horowitz, "An eight channel 35 GSample/s CMOS timing analyzer," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2000, pp. 170-171.
3. L.-M. Lee and C.-K. K. Yang, "A sub-10ps multi-phase sampling system using redundancy," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2005, pp. 510-613.
4. M. Takamiya, H. Inohara, and M. Mizuno, "On-chip jitter-spectrum-analyzer for high-speed digital designs," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2004, pp. 350-351.
5. R. Kuppuswamy et al., "On-die clock jitter detector for high speed microprocessors," in Symp. VLSI Circuits Dig. Tech. Papers. Jun. 2001, pp. 187-191.
6. K. A. Jenkins, A. P. Jose, and D. F. Heidel, "An on-chip jitter measurement circuit with sub-picosecond resolution," in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2005, pp. 157-160.
7. P. Dudek, S. Szczepanski, and J. V. Hatfield, "A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line," IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 240-247, Feb. 2000.
8. P. J. Restle, R. L. Franch, N. K. James, W. V. Huott, T. M. Skergan, S. C. Wilson, N. S. Schwartz, and J. G. Clabes, "Timing uncertainty measurements on the Power5 microprocessor," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2004, pp. 354-355.
9. K. Nose, M. Kajita, and M. Mizuno, "A 1ps-resolution jitter-measurement macro using interpolated jitter oversampling," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, pp. 520-521.