A high-precision time-to-digital converter using a two-level conversion scheme

IEEE Transactions on Nuclear Science

Volumn 51, Issue 4 I, 2004, Pages 1349-1352

  Hwang, Chorng Sii ^a   Chen, Poki ^b   Tsao, Hen Wai ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

Author keywords

Delay locked loop; Time to digital converter (TDC); Vernier delay line

Indexed keywords

DELAY-LOCKED LOOPS; LOOP FILTERS; TIME-TO-DIGITAL CONVERTOR (TDC); VERNIER DELAY LINE (VDL);

COMPUTER SIMULATION; CONTROL NONLINEARITIES; CONTROL SYSTEM ANALYSIS; DESIGN AIDS; GRAPH THEORY; INFORMATION ANALYSIS; MATHEMATICAL MODELS; SIGNAL PROCESSING; TIME AND MOTION STUDY; VOLTAGE MEASUREMENT;

ANALOG TO DIGITAL CONVERSION;

EID: 4444324969     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2004.832902     Document Type: Conference Paper

References (5)

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