-
1
-
-
17044440047
-
Cellular handset integration - SIP vs. SOC
-
Oct.
-
W. Krenik, D. Buss, and P. Rickert, "Cellular handset integration - SIP vs. SOC," in Proc. IEEE Custom Integrated Circuits Conf., Oct. 2004, pp. 63-70.
-
(2004)
Proc. IEEE Custom Integrated Circuits Conf.
, pp. 63-70
-
-
Krenik, W.1
Buss, D.2
Rickert, P.3
-
2
-
-
14844298187
-
RF CMOS comes of age
-
Apr.
-
A. A. Abidi, "RF CMOS comes of age," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 549-561, Apr. 2004.
-
(2004)
IEEE J. Solid-state Circuits
, vol.39
, Issue.4
, pp. 549-561
-
-
Abidi, A.A.1
-
3
-
-
2442678899
-
All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13 μm CMOS
-
Feb.
-
B. Staszewski, C.-M. Hung, K. Maggio, J. Wallberg, D. Leipold, and P. Balsara, "All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13 μm CMOS," in Proc. IEEE Solid-State Circuits Conf., Feb. 2004, pp. 272-273.
-
(2004)
Proc. IEEE Solid-state Circuits Conf.
, pp. 272-273
-
-
Staszewski, B.1
Hung, C.-M.2
Maggio, K.3
Wallberg, J.4
Leipold, D.5
Balsara, P.6
-
4
-
-
24944538548
-
All-digital PLL and GSM/EDGE transmitter in 90 nm CMOS
-
Feb.
-
R. B. Staszewski, J. Wallberg, S. Rezeq, C.-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, "All-digital PLL and GSM/EDGE transmitter in 90 nm CMOS," in Proc. IEEE Solid-State Circuits Conf., Feb. 2005, pp. 316-317.
-
(2005)
Proc. IEEE Solid-state Circuits Conf.
, pp. 316-317
-
-
Staszewski, R.B.1
Wallberg, J.2
Rezeq, S.3
Hung, C.-M.4
Eliezer, O.5
Vemulapalli, S.6
Fernando, C.7
Maggio, K.8
Staszewski, R.9
Barton, N.10
Lee, M.-C.11
Cruise, P.12
Entezari, M.13
Muhammad, K.14
Leipold, D.15
-
5
-
-
10444256218
-
Quad-band GSM/GPRS/EDGE polar loop transmitter
-
Dec.
-
T. Sowlati, D. Rozenblit, R. Pullela, M. Damgaard, E. McCarthy, D. Koh, D. Ripley, F. Balteanu, and I. Gheorghe, "Quad-band GSM/GPRS/EDGE polar loop transmitter," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2179-2189, Dec. 2004.
-
(2004)
IEEE J. Solid-state Circuits
, vol.39
, Issue.12
, pp. 2179-2189
-
-
Sowlati, T.1
Rozenblit, D.2
Pullela, R.3
Damgaard, M.4
McCarthy, E.5
Koh, D.6
Ripley, D.7
Balteanu, F.8
Gheorghe, I.9
-
6
-
-
10444225405
-
A polar modulator transmitter for GSM/EDGE
-
Dec.
-
M. R. Elliott, T. Montalvo, B. P. Jeffries, F. Murden, J. Strange, A. Hill, S. Nandipaku, and J. Harrebek, "A polar modulator transmitter for GSM/EDGE," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2190-2199, Dec. 2004.
-
(2004)
IEEE J. Solid-state Circuits
, vol.39
, Issue.12
, pp. 2190-2199
-
-
Elliott, M.R.1
Montalvo, T.2
Jeffries, B.P.3
Murden, F.4
Strange, J.5
Hill, A.6
Nandipaku, S.7
Harrebek, J.8
-
7
-
-
0041589316
-
A first digitally-controlled oscillator in a deep-submicron CMOS process for multi-GHz wireless applications
-
Jun.
-
R. B. Staszewski, D. Leipold, C.-M. Hung, and P. T. Balsara, "A first digitally-controlled oscillator in a deep-submicron CMOS process for multi-GHz wireless applications," in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symp., Jun. 2003, pp. 81-84.
-
(2003)
Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symp.
, pp. 81-84
-
-
Staszewski, R.B.1
Leipold, D.2
Hung, C.-M.3
Balsara, P.T.4
-
8
-
-
0344512371
-
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process
-
Nov.
-
R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara, "Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 11, pp. 815-828, Nov. 2003.
-
(2003)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.
, vol.50
, Issue.11
, pp. 815-828
-
-
Staszewski, R.B.1
Leipold, D.2
Muhammad, K.3
Balsara, P.T.4
-
9
-
-
0344512370
-
Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation
-
Nov.
-
R. B. Staszewski, D. Leipoli, and P. T. Balsara, "Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation," IEEE Trans. Circuits Syst. Il, Analog Digit. Signal Process., vol. 50, no. 11, pp 887-892, Nov. 2003.
-
(2003)
IEEE Trans. Circuits Syst. Il, Analog Digit. Signal Process.
, vol.50
, Issue.11
, pp. 887-892
-
-
Staszewski, R.B.1
Leipoli, D.2
Balsara, P.T.3
-
10
-
-
10444260492
-
All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS
-
Dec.
-
R. B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J. L. Wallberg, C. Fernando, K Maggio, R. Staszewski, T. Jung, J. Koh, S. John, I. Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O. E. Eliezer, E. de-Obaldia, and P. T. Balsara, "All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS, " IEEE J, Solid-State Circuits, vol. 39, no. 12, pp. 2278-2291, Dec. 2004.
-
(2004)
IEEE J, Solid-state Circuits
, vol.39
, Issue.12
, pp. 2278-2291
-
-
Staszewski, R.B.1
Muhammad, K.2
Leipold, D.3
Hung, C.-M.4
Ho, Y.-C.5
Wallberg, J.L.6
Fernando, C.7
Maggio, K.8
Staszewski, R.9
Jung, T.10
Koh, J.11
John, S.12
Deng, I.Y.13
Sarda, V.14
Moreira-Tamayo, O.15
Mayega, V.16
Katz, R.17
Friedman, O.18
Eliezer, O.E.19
De-Obaldia, E.20
Balsara, P.T.21
more..
-
11
-
-
2442647552
-
A discrete-time Bluetooth receiver in a 0.13 μm digital CMOS process
-
Feb.
-
K. Muhammad, D. Leipold B. Staszewski, Y.-C. Ho, C.-M. Hung, K. Maggio, C. Fernando, T. Jung, J. Wallberg, J.-S. Koh, S. John, I. Deng, O. Moreira, R. Staszewski, R Katz, and O. Friedman, "A discrete-time Bluetooth receiver in a 0.13 μm digital CMOS process," in Proc. IEEE Solid-State Circuits Conf., Feb. 2004, pp. 268-269.
-
(2004)
Proc. IEEE Solid-state Circuits Conf.
, pp. 268-269
-
-
Muhammad, K.1
Leipold, D.2
Staszewski, B.3
Ho, Y.-C.4
Hung, C.-M.5
Maggio, K.6
Fernando, C.7
Jung, T.8
Wallberg, J.9
Koh, J.-S.10
John, S.11
Deng, I.12
Moreira, O.13
Staszewski, R.14
Katz, R.15
Friedman, O.16
-
13
-
-
18144411685
-
Event-driven simulation and modeling of pha se noise of an RF oscillator
-
Apr.
-
R. B. Staszewski, C. Fernar do, and P. T. Balsara, "Event-driven simulation and modeling of pha se noise of an RF oscillator," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 4, pp. 723-733, Apr. 2005.
-
(2005)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.52
, Issue.4
, pp. 723-733
-
-
Staszewski, R.B.1
Fernardo, C.2
Balsara, P.T.3
-
14
-
-
0029695737
-
A minimal multibit digital noise shapi ig architecture
-
S. R. Norsworthy, D. A. Rich, and T. R. Viswanathan, "A minimal multibit digital noise shapi ig architecture," in Proc. IEEE Int. Symp. Circuits and Systems, 1996, pp. 5-8.
-
(1996)
Proc. IEEE Int. Symp. Circuits and Systems
, pp. 5-8
-
-
Norsworthy, S.R.1
Rich, D.A.2
Viswanathan, T.R.3
-
15
-
-
0035696224
-
A filtering technique to lower LC oscillator phase noise
-
Dec.
-
E. Hegazi, H. Sjoland, and A. A. Abidi, "A filtering technique to lower LC oscillator phase noise,"IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, Dec. 2001.
-
(2001)
IEEE J. Solid-state Circuits
, vol.36
, Issue.12
, pp. 1921-1930
-
-
Hegazi, E.1
Sjoland, H.2
Abidi, A.A.3
-
16
-
-
0242573743
-
A first multigigahertz digitally controlled oscillator for wireless applications
-
Nov.
-
R. B. Staszewski, C.-M. Hung, D. Leipold, and P. T. Balsara, "A first multigigahertz digitally controlled oscillator for wireless applications," IEEE Trans. Microw. Theory Tech., vol. 51, no. 11, pp. 2154-2164, Nov. 2003.
-
(2003)
IEEE Trans. Microw. Theory Tech.
, vol.51
, Issue.11
, pp. 2154-2164
-
-
Staszewski, R.B.1
Hung, C.-M.2
Leipold, D.3
Balsara, P.T.4
-
18
-
-
0026943172
-
A new PLL frequency synthesizer with high switching speed
-
Nov.
-
A. Kajiwara and M. Nakagawa, "A new PLL frequency synthesizer with high switching speed," IEEE Trans. Veh. Technol., vol. 41, no. 4, pp. 407-413, Nov. 1992.
-
(1992)
IEEE Trans. Veh. Technol.
, vol.41
, Issue.4
, pp. 407-413
-
-
Kajiwara, A.1
Nakagawa, M.2
-
19
-
-
15944399705
-
Phase-domain all-digital phaselocked loop
-
Mar.
-
R. B. Staszewski and P. T. Balsara, "Phase-domain all-digital phaselocked loop," IEEE Trans. circuits Syst. II, Exp. Briefs, vol. 52, no. 3, pp. 159-163, Mar. 2005.
-
(2005)
IEEE Trans. Circuits Syst. II, Exp. Briefs
, vol.52
, Issue.3
, pp. 159-163
-
-
Staszewski, R.B.1
Balsara, P.T.2
-
20
-
-
0024104186
-
z-domain model for discrete-time PLL's
-
Nov.
-
J. P. Hein and J. W. Scott, "z-domain model for discrete-time PLL's," IEEE Trans. Circuits Syst., vol. 35, no. 11, pp. 1393-1400, Nov. 1988.
-
(1988)
IEEE Trans. Circuits Syst.
, vol.35
, Issue.11
, pp. 1393-1400
-
-
Hein, J.P.1
Scott, J.W.2
-
21
-
-
4444331072
-
TDC-based frequency synthesizer for wireless applications
-
Jun.
-
R. B. Staszewski, D. Leipold, C.-M. Hung, and P. T. Balsara, "TDC-based frequency synthesizer for wireless applications," in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symp., Jun. 2004, pp. 215-218.
-
(2004)
Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symp.
, pp. 215-218
-
-
Staszewski, R.B.1
Leipold, D.2
Hung, C.-M.3
Balsara, P.T.4
|