Nonlinearity correction of the integrated time-to-digital converter with direct coding

IEEE Transactions on Instrumentation and Measurement

Volumn 46, Issue 2, 1997, Pages 449-453

  Pelka, Ryszard ^a,b   Kalisz, Jozef ^a,b   Szplet, Ryszard ^b  

^a IEEE   (Poland)

^b MILITARY UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR ANALYSIS; ERROR CORRECTION; MATHEMATICAL MODELS; NEURAL NETWORKS; STATISTICAL METHODS;

FIELD PROGRAMMABLE GATE ARRAY (FPGA) DEVICES; LEAST SIGNIFICANT BIT (LSB); LEVENBERG MARQUARDT (LM) LEARNING RULE; NONLINEARITY ERRORS; TIME TO DIGITAL CONVERTERS (TDC);

CODE CONVERTERS;

EID: 0031117760     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/19.571882     Document Type: Article

References (8)

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2. J. Kalisz, R. Szplet, R. Pelka, and A. Poniecki, "Single-chip interpolating time counter with 200-ps resolution and 43-s range," in Proc. IEEE Instrum. Meas. Tech. Conf. IMTC'96, Brussels, June 4-6, 1996, vol. 1, pp. 676-680.
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